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    Loss of signal detection circuit
    11.
    发明授权
    Loss of signal detection circuit 有权

    公开(公告)号：US10763841B2

    公开(公告)日：2020-09-01

    申请号：US16535557

    申请日：2019-08-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Huanzhang Huang ,  Amit Rane

    IPC: G06F13/38 ,  H03K17/00 ,  H03K19/003 ,  H03K17/56

    Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

    Embedded universal serial bus 2 repeater
    12.
    发明授权
    Embedded universal serial bus 2 repeater 有权

    公开(公告)号：US10762016B2

    公开(公告)日：2020-09-01

    申请号：US16404494

    申请日：2019-05-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing Maung ,  Douglas Edward Wente ,  Mustafa Ulvi Erdogan ,  Huanzhang Huang ,  Saurabh Goyal ,  Bhupendra Sharma

    IPC: G06F13/38 ,  G06F13/42 ,  H04B3/36

    Abstract: Aspects of the disclosure provide for a circuit including a squelch detector having a first input coupled to a first node and configured to receive a positive component of a differential signal with a floating center tap, a second input coupled to a second node and configured to receive a negative component of the differential signal, and an output coupled to a logic circuit, a first resistor coupled between the first node and a third node, a second resistor coupled between the third node and the second node, a third resistor coupled between the first node and a fourth node, a fourth resistor coupled between the fourth node and the second node, a capacitor coupled between the fourth node and a ground terminal, a comparator having a first input coupled to the third node, a second input coupled to a fifth node, and an output coupled to the logic circuit.

    CLOSED-LOOP HIGH-SPEED CHANNEL EQUALIZER ADAPTATION
    14.
    发明申请
    CLOSED-LOOP HIGH-SPEED CHANNEL EQUALIZER ADAPTATION 审中-公开
    闭环高速通道均衡器适配

    公开(公告)号：US20150341194A1

    公开(公告)日：2015-11-26

    申请号：US14819239

    申请日：2015-08-05

    Applicant: Texas Instruments Incorporated

    Inventor： Roland Sperlich ,  Huanzhang Huang ,  Charles M. Branch

    IPC: H04L27/01 ,  H04L25/03

    CPC classification number: H04L27/01 ,  H04B3/144 ,  H04L25/026 ,  H04L25/03019 ,  H04L25/03885

    Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

    Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。

    Adjustable embedded universal serial bus 2 low-impedance driving duration
    15.
    发明授权
    Adjustable embedded universal serial bus 2 low-impedance driving duration 有权

    公开(公告)号：US11068428B2

    公开(公告)日：2021-07-20

    申请号：US16414496

    申请日：2019-05-16

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Win Naing Maung ,  Yonghui Tang ,  Huanzhang Huang ,  Douglas Edward Wente

    IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42

    Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

    Differential driver with pull up and pull down boosters
    17.
    发明授权
    Differential driver with pull up and pull down boosters 有权

    公开(公告)号：US09660652B2

    公开(公告)日：2017-05-23

    申请号：US14847264

    申请日：2015-09-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Weicheng Zhang ,  Huanzhang Huang ,  Yanli Fan ,  Roland Sperlich

    IPC: H03K17/16 ,  H03K19/0944

    CPC classification number: H03K19/0944 ,  H03K19/018578

    Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

    Differential receiver
    18.
    发明授权
    Differential receiver 有权
    差分接收机

    公开(公告)号：US09337789B2

    公开(公告)日：2016-05-10

    申请号：US14048750

    申请日：2013-10-08

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Weicheng Zhang ,  Huanzhang Huang ,  Yanli Fan ,  Mark W. Morgan

    IPC: H03F3/45

    CPC classification number: H03F3/45219 ,  H03F3/45632 ,  H03F2203/45466 ,  H03F2203/45646 ,  H03F2203/45648

    Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

    Abstract translation: 具有降低的共模感应传播延迟方差的差分接收机。 差分接收机的一个实施方式包括第一差分放大器，第二差分放大器和第一电流源。 第一差分放大器包括第一晶体管对。 第二差分放大器包括第二晶体管对。 第一电流源耦合到第一晶体管对的第一晶体管的漏极节点。 第一电流源被配置为根据第一差分放大器的可变尾电流和第二差分放大器的可变尾电流的和的函数，在漏极节点处产生可变的第一电流。

    CLOSED-LOOP HIGH-SPEED CHANNEL EQUALIZER ADAPTATION
    19.
    发明申请
    CLOSED-LOOP HIGH-SPEED CHANNEL EQUALIZER ADAPTATION 有权
    闭环高速通道均衡器适配

    公开(公告)号：US20140362900A1

    公开(公告)日：2014-12-11

    申请号：US14299187

    申请日：2014-06-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Roland Sperlich ,  Huanzhang Huang ,  Charles M. Branch

    IPC: H04L27/01

    CPC classification number: H04L27/01 ,  H04B3/144 ,  H04L25/026 ,  H04L25/03019 ,  H04L25/03885

    Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

    Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。

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