Abstract:
Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.
Abstract:
Triggered remote function calls can be used in master-slave systems to trigger slave-side software functions pre-loaded by a master into slave MCU memory, with associated parameters pre-loaded into a slave function interface memory. A master issues trigger-function signals (such as rising/falling edges or signal levels) over a trigger-function signal line. The slave includes a trigger conditioning block that in response issues a trigger-function request to the slave MCU, which calls/executes the associated software function, including accessing the associated trigger-function parameters from function interface memory. A slave can include a hardware function block with functionality configurable by a pre-loaded software configuration function (with associated parameters). A master can include a hardware function block configured to issue trigger-function signals. The slave (trigger conditioning block) can be configured to service trigger-function signals as an IRQ (interrupt request) to the MCU, which executes an ISR (interrupt service routine) as a triggered function call.
Abstract:
A phase rotator corrects the IQ imbalance in a wireless transceiver. The phase rotator is a part of a compensation system that detects and separates reception impairment images from transmission impairment images. The disclosed phase rotator introduces a phase shift between the transmission channel and the reception channel without perturbing the phase mismatch and the gain mismatch in the reception path. The phase rotator includes a first local oscillation (LO) circuit that generates a first LO signal at a first carrier frequency and a second LO circuit that generates a second LO signal at a second carrier frequency that deviates from the first carrier frequency for a phase rotation period. The phase rotation period is sufficiently long such that the frequency deviation can introduce a prescribed phase shift between the first LO signal and the second LO signal.
Abstract:
A direct conversion wireless transceiver is configured for TX/FBRX sequential QMC calibration (coefficient generation) using separate/shared PLLs. A TX LO drives upconversion, and an RX LO drives downconversion. TX/RX digital QMC compensators compensate for IQ mismatch (with optional DPD compensation), and QMC calibration is used to calibrate the TX/RX QMC filter coefficients based on a QMC calibration procedure. The TX LO signal source is a TX PLL, and the RX LO signal source is selectively the TX PLL or a separate FBRX PLL. A QMC controller performs QMC calibration to generate calibrated TX/FBRX QMC filter coefficients, including: disconnecting the TX PLL from, and connecting the FBRX PLL to, the RX LO; generating calibrated TX QMC filter coefficients; generating calibrated FBRX QMC filter coefficients; disconnecting the FBRX PLL from, and connecting the TX PLL to, the RX LO; generating re-calibrated FBRX QMC filter coefficients.
Abstract:
Systems and methods for phase alignment among multiple transmitters are described. In some embodiments, a method may include creating a loop between an RF transmitter and an RF receiver; measuring a first DC signal on the I and Q paths of the RF receiver without inserting a DC signal in the I and Q paths of the RF transmitter; measuring a second DC signal on the I and Q paths of the RF receiver while inserting a non-zero DC signal in the I and Q paths of the RF transmitter; and calculating a relative phase difference between the RF transmitter and the RF receiver using the first and second DC signals.
Abstract:
A direct conversion wireless transceiver is configured for TX/FBRX sequential QMC calibration (coefficient generation) using separate/shared PLLs. A TX LO drives upconversion, and an RX LO drives downconversion. TX/RX digital QMC compensators compensate for IQ mismatch (with optional DPD compensation), and QMC calibration is used to calibrate the TX/RX QMC filter coefficients based on a QMC calibration procedure. The TX LO signal source is a TX PLL, and the RX LO signal source is selectively the TX PLL or a separate FBRX PLL. A QMC controller performs QMC calibration to generate calibrated TX/FBRX QMC filter coefficients, including: disconnecting the TX PLL from, and connecting the FBRX PLL to, the RX LO; generating calibrated TX QMC filter coefficients; generating calibrated FBRX QMC filter coefficients; disconnecting the FBRX PLL from, and connecting the TX PLL to, the RX LO; generating re-calibrated FBRX QMC filter coefficients.