公开(公告)号：US09029251B2

公开(公告)日：2015-05-12

申请号：US14451485

申请日：2014-08-05

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Jarvis Benjamin Jacobs ,  Ajith Varghese

IPC: H01L21/425 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L21/324 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/105 ,  H01L29/66477

Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

公开(公告)号：US20140339609A1

公开(公告)日：2014-11-20

申请号：US14451489

申请日：2014-08-05

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Jarvis Benjamin Jacobs ,  Ajith Varghese

IPC: H01L21/324 ,  H01L21/265 ,  H01L21/8234

CPC classification number: H01L21/324 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/105 ,  H01L29/66477

Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

公开(公告)号：US12015057B2

公开(公告)日：2024-06-18

申请号：US17156612

申请日：2021-01-24

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Alexei Sadovnikov ,  Henry Litzmann Edwards ,  Jarvis Benjamin Jacobs

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/26 ,  H01L29/66

CPC classification number: H01L29/26 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: A semiconductor device including drain extended metal oxide semiconductor field effect transistor (MOSFET) includes a source region and a drain region each having a first dopant type spaced apart along a surface of a semiconductor material having a second opposite conductivity type. A gate electrode over the semiconductor material surface between the source region and the drain region. A diffusion suppression implant region in the semiconductor material extends from the source region under the gate electrode. The diffusion suppression implant region includes a body region having the second opposite conductivity type and comprises at least one of carbon, nitrogen, and fluorine.

公开(公告)号：US11121207B2

公开(公告)日：2021-09-14

申请号：US15348459

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Abbas Ali ,  Sopa Chevacharoenkul ,  Jarvis Benjamin Jacobs

IPC: H01L49/02 ,  H01L21/762 ,  H01L21/265 ,  H01L21/308

Abstract: A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.

公开(公告)号：US20190207010A1

公开(公告)日：2019-07-04

申请号：US15859492

申请日：2017-12-30

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Michael Allen Ball ,  Jarvis Benjamin Jacobs ,  James Robert Todd

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/02 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/762 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L29/665 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/32137 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/4175 ,  H01L29/456

Abstract: An integrated circuit having silicide block integrated with CMOS transistors is formed by forming a silicide block layer of primarily silicon dioxide, free of silicon nitride and silicon oxy-nitride, at less than 400° C. prior to annealing the PMOS sources and drains. A spike anneal process concurrently anneals the PMOS sources and drains and densifies the silicide block layer. The NMOS drain junctions are less than 120 nanometers; the NMOS halo regions include boron. The NMOS and PMOS transistors are laterally separated by an STI oxide layer. A wet deglaze process prior to metal silicide formation removes less than 25 percent of the silicide block layer, and exposes sides of the NMOS drains less than 20 percent of the drain junction depth. The metal silicide does not extend down the NMOS drains sides, directly adjacent to the STI oxide layer, more than 20 percent of the drain junction depth.

公开(公告)号：US20160308007A1

公开(公告)日：2016-10-20

申请号：US15191656

申请日：2016-06-24

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Jarvis Benjamin Jacobs

IPC: H01L29/40

CPC classification number: H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

Abstract translation: 半导体器件通过在衬底中形成深沟槽和在深沟槽的侧壁上形成介电衬垫来形成。 第一未掺杂多晶硅层形成在半导体器件上，延伸到电介质衬垫上的深沟槽中，但不填充深沟槽。 将掺杂剂注入到第一多晶硅层中。 在第一多晶硅层上形成第二层多晶硅。 热驱动退火激活并扩散掺杂剂。 在一个版本中，在形成第一多晶硅层之前，在深沟槽的底部去除电介质衬垫，使得深沟槽中的多晶硅提供与衬底的接触。 在另一种形式中，深沟槽中的多晶硅通过电介质衬垫从衬底隔离。

公开(公告)号：US09401410B2

公开(公告)日：2016-07-26

申请号：US14555300

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer P Pendharkar ,  Jarvis Benjamin Jacobs

IPC: H01L21/8242 ,  H01L29/45 ,  H01L49/02 ,  H01L29/41 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

Abstract translation: 半导体器件通过在衬底中形成深沟槽和在深沟槽的侧壁上形成介电衬垫来形成。 第一未掺杂多晶硅层形成在半导体器件上，延伸到电介质衬垫上的深沟槽中，但不填充深沟槽。 将掺杂剂注入到第一多晶硅层中。 在第一多晶硅层上形成第二层多晶硅。 热驱动退火激活并扩散掺杂剂。 在一个版本中，在形成第一多晶硅层之前，在深沟槽的底部去除电介质衬垫，使得深沟槽中的多晶硅提供与衬底的接触。 在另一种形式中，深沟槽中的多晶硅通过电介质衬垫从衬底隔离。

公开(公告)号：US20160149011A1

公开(公告)日：2016-05-26

申请号：US14555300

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Jarvis Benjamin Jacobs

IPC: H01L29/45 ,  H01L29/41 ,  H01L21/225 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/324 ,  H01L49/02 ,  H01L21/02

CPC classification number: H01L29/41 ,  H01L21/02164 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/32155 ,  H01L21/324 ,  H01L21/743 ,  H01L21/763 ,  H01L28/20 ,  H01L28/40 ,  H01L29/407 ,  H01L29/45 ,  H01L29/945

Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.