公开(公告)号：US09281213B2

公开(公告)日：2016-03-08

申请号：US14576736

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： John Paul Campbell ,  Kaiping Liu

IPC: H01L21/28 ,  H01L21/321 ,  H01L49/02 ,  H01L21/285 ,  H01L21/3213

CPC classification number: H01L28/60 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/0273 ,  H01L21/28035 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/3211 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/0629

Abstract: A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre- and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric.

公开(公告)号：US08975135B2

公开(公告)日：2015-03-10

申请号：US14301766

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Kaiping Liu ,  Amitava Chatterjee ,  Imran Mahmood Khan

IPC: H01L21/8242 ,  H01L29/66 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L29/66181 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11558 ,  H01L28/60

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.

Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 由氮化硅顶层下面的二氧化硅层构成的硅化物阻挡膜阻止在电极上形成硅化物包层，而诸如多晶硅对金属电容器的集成电路中的其它多晶硅结构是硅化物 - 包裹 在硅化之后，在剩余的多晶硅结构上沉积电容器电介质，随后形成上部金属板。