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    Dynamic power reduction and performance improvement in caches using fast access
    12.
    发明授权
    Dynamic power reduction and performance improvement in caches using fast access 有权

    公开(公告)号：US09652397B2

    公开(公告)日：2017-05-16

    申请号：US14694415

    申请日：2015-04-23

    Applicant: Texas Instruments Incorporated

    Inventor： Oluleye Olorode ,  Mehrdad Nourani

    IPC: G06F12/08 ,  G06F12/0864

    CPC classification number: G06F12/0864 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/6032 ,  Y02D10/13

    Abstract: With the increasing demand for improved processor performance, memory systems have been growing increasingly larger to keep up with this performance demand. Caches, which dictate the performance of memory systems are often the focus of improved performance in memory systems, and the most common techniques used to increase cache performance are increased size and associativity. Unfortunately, these methods yield increased static and dynamic power consumption. In this invention, a technique is shown that reduces the power consumption in associative caches with some improvement in cache performance. The architecture shown achieves these power savings by reducing the number of ways queried on each cache access, using a simple hash function and no additional storage, while skipping some pipe stages for improved performance. Up to 90% reduction in power consumption with a 4.6% performance improvement was observed.

    Local page translation and permissions storage for the page window in program memory controller
    13.
    发明授权
    Local page translation and permissions storage for the page window in program memory controller 有权
    程序存储控制器中的页面窗口的本地页面转换和权限存储

    公开(公告)号：US09514058B2

    公开(公告)日：2016-12-06

    申请号：US14579641

    申请日：2014-12-22

    Applicant: Texas Instruments Incorporated

    Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

    IPC: G06F12/00 ,  G06F12/10

    CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/65 ,  Y02D10/13

    Abstract: This invention provides a current page translation register storing virtual to physical address translation data for a single current page and optionally access permission data for the same page for program accesses. If an accessed address is within the current page, the address translation and permission data is accessed from current page translation register. This current page translation register provides an additional level of caching of this data above the typical translation look-aside buffer and micro translation look-aside buffer. The smaller size of the current page translation register provides faster page hit/miss determination and faster data access using less power than the typical architecture. This is helpful for program access which generally hits the current page more frequently than data access.

    Abstract translation: 本发明提供了当前的页面翻译寄存器，其存储用于单个当前页面的虚拟到物理地址转换数据，并且可选地访问用于程序访问的同一页面的许可数据。 如果访问的地址在当前页面内，则从当前页面翻译寄存器访问地址转换和许可数据。 这个当前的页面翻译寄存器提供了这种数据的高级缓存，这些数据在典型的翻译后备缓冲区和微型翻译后备缓冲区之上。 当前页面翻译寄存器的较小尺寸使用比典型架构更少的功率提供更快的页面命中/错误确定和更快的数据访问。 这对于通常比数据访问更频繁地访问当前页面的程序访问是有帮助的。

    Hiding Page Translation Miss Latency in Program Memory Controller By Selective Page Miss Translation Prefetch
    14.
    发明申请
    Hiding Page Translation Miss Latency in Program Memory Controller By Selective Page Miss Translation Prefetch 有权
    隐藏页面翻译小计延迟在程序存储器控制器通过选择性页面小姐翻译预取

    公开(公告)号：US20160179700A1

    公开(公告)日：2016-06-23

    申请号：US14579654

    申请日：2014-12-22

    Applicant: Texas Instruments Incorporated

    Inventor： Ramakrishnan Venkatasubramanian ,  Oluleye Olorode ,  Bipin Prasad Heremagalur Ramaprasad

    IPC: G06F12/10

    CPC classification number: G06F12/1045 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/654 ,  G06F2212/681

    Abstract: This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU, the L1I cache controller does a-priori lookup of whether the virtual address plus the fetch packet count of expected program fetches crosses a page boundary. If the access crosses a page boundary, the L1I cache controller will request a second page translation along with the first page. This pipelines requests to the μTLB without waiting for L1I cache controller to begin processing the second page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored locally in L1I cache controller and used when the access crosses the page boundary.

    Abstract translation: 本发明隐藏程序提取的页面未命中转换延迟。 在本发明中，只要CPU请求访问，L1I高速缓存控制器先验地查看虚拟地址加上预期程序提取的提取数据包数是否跨越页边界。 如果访问跨页面边界，则L1I缓存控制器将与第一页一起请求第二页翻译。 该管道请求到μTLB，而不等待L1I缓存控制器开始处理第二页请求。 这成为第二页翻译请求的确定性预取。 第二页的翻译信息本地存储在L1I高速缓存控制器中，当访问越过页面边界时使用。

    Local Page Translation and Permissions Storage for the Page Window in Program Memory Controller
    15.
    发明申请
    Local Page Translation and Permissions Storage for the Page Window in Program Memory Controller 有权
    程序存储器控制器中的页面窗口的本地页面翻译和权限存储

    公开(公告)号：US20160179695A1

    公开(公告)日：2016-06-23

    申请号：US14579641

    申请日：2014-12-22

    Applicant: Texas Instruments Incorporated

    Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/65 ,  Y02D10/13

    Abstract: This invention provides a current page translation register storing virtual to physical address translation data for a current page and optionally access permission data for the same page for program accesses. If an accessed address is within the current page, the address translation and permission data is accessed from current page translation register. This current page translation register provides an additional level of caching of this data above the typical translation look-aside buffer and micro translation look-aside buffer. The smaller size of the current page translation register provides faster page hit/miss determination and faster data access using less power than the typical architecture. This is helpful for program access which generally hits the current page more frequently than data access.

    Abstract translation: 本发明提供了当前页面转换寄存器，其存储用于当前页面的虚拟到物理地址转换数据，并且可选地访问用于程序访问的同一页面的许可数据。 如果访问的地址在当前页面内，则从当前页面翻译寄存器访问地址转换和许可数据。 这个当前的页面翻译寄存器提供了这种数据的高级缓存，这些数据在典型的翻译后备缓冲区和微型翻译后备缓冲区之上。 当前页面翻译寄存器的较小尺寸使用比典型架构更少的功率提供更快的页面命中/错误确定和更快的数据访问。 这对于通常比数据访问更频繁地访问当前页面的程序访问是有帮助的。

    ZERO LATENCY PREFETCHING IN CACHES
    17.
    发明申请
    ZERO LATENCY PREFETCHING IN CACHES 有权

    公开(公告)号：US20250103503A1

    公开(公告)日：2025-03-27

    申请号：US18976568

    申请日：2024-12-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian ,  Hung Ong

    IPC: G06F12/0862 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0888 ,  G06F12/1027

    Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetchs the lower half level two cache line employing fewer resources than an ordinary prefetch.

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