公开(公告)号：US20230378146A1

公开(公告)日：2023-11-23

申请号：US18320102

申请日：2023-05-18

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Julian Carlo Barbadillo ,  Chun Ping Lo ,  Sylvester Ankamah-Kusi ,  Rajen Murugan ,  Thomas Kronenberg ,  Jonathan Noquil ,  Guangxu Li ,  Blake Travis ,  Jason Colte

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/16 ,  H01L23/49822 ,  H01L28/40 ,  H01L23/3121 ,  H01L24/16 ,  H01L23/49562 ,  H01L21/4857 ,  H01L21/56 ,  H01L2224/16227

Abstract: An example microelectronic device package includes: a multilayer package substrate comprising routing conductors spaced by dielectric material, the multilayer package substrate having a device side surface and an opposing board side surface, and having a recessed portion extending from the device side surface and exposing routing conductors beneath the device side surface of the multilayer package substrate; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to the routing conductors; a passive component mounted to the routing conductors exposed in the recessed portion of the multilayer package substrate; and mold compound covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.

公开(公告)号：US20230352850A1

公开(公告)日：2023-11-02

申请号：US18309720

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Harshpreet Singh Phull Bakshi ,  Sylvester Ankamah-Kusi ,  Juan Herbsommer ,  Aditya Nitin Jogalekar

IPC: H01Q21/00 ,  H01Q1/22

CPC classification number: H01Q21/005 ,  H01Q1/2283

Abstract: An example microelectronic device package includes: a multilayer package substrate including a slotted waveguide antenna and having routing conductors, the multilayer package substrate having a device side surface and an opposing board side surface; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to slotted waveguide antenna by the routing conductors; and mold compound covering the semiconductor die, and a portion of the multilayer package substrate.

公开(公告)号：US20230352314A1

公开(公告)日：2023-11-02

申请号：US17733998

申请日：2022-04-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Phuong Minh Vu ,  Sylvester Ankamah-Kusi

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L21/485 ,  H01L23/3121 ,  H01L23/49838 ,  H01L24/16 ,  H01L21/56 ,  H01L2224/16227

Abstract: Described examples include a method having steps of laying out at least two conductors and modeling conductor current through the at least two conductors to determine a current density in the at least two conductors. The method also has steps of revising the at least two conductors as adjusted conductors to add conductive material to areas of the conductor where the modeling conductor current shows above average current density; fabricating the adjusted conductors; and mounting a die to the adjusted conductors.

公开(公告)号：US20240304517A1

公开(公告)日：2024-09-12

申请号：US18180024

申请日：2023-03-07

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Jie Chen ,  Yutaka Suzuki ,  Rajen Murugan

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/784 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/3737 ,  H01L21/565 ,  H01L21/784 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/165 ,  H01L2224/08235 ,  H01L2224/273 ,  H01L2224/29193 ,  H01L2224/32221 ,  H01L2224/94 ,  H01L2924/182

Abstract: An electronic device includes: a semiconductor die having opposite first and second sides and a conductive terminal along the first side; a conductive lead electrically coupled to the conductive terminal; a package structure that forms a top side of the electronic device and encloses a portion of the semiconductor die, the package structure including a first molding compound having a first thermal conductivity; and a thermally conductive layer on at least a portion of the second side of the semiconductor die, the thermally conductive layer including a second molding compound having a second thermal conductivity that is greater than the first thermal conductivity.

公开(公告)号：US20240128170A1

公开(公告)日：2024-04-18

申请号：US17965583

申请日：2022-10-13

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Li Jiang ,  Rajen Murugan ,  Robert John Falcone ,  Usman Mahmood Chaudhry

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/373 ,  H01L23/66

CPC classification number: H01L23/49805 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3736 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2223/6688

Abstract: An electronic device includes a rectangular ceramic package structure having opposite first and second sides, an interior cavity that extends to an opening in the second side, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, and non-conductive indents extending into the third and fourth sides. The device also includes a semiconductor die in the cavity, a lid that covers the opening and seals the cavity, a conductive terminal having a planar side exposed along the first side that is electrically coupled to a circuit of the semiconductor die and extends to a first one of the non-conductive indents, and conductive pins spaced apart from the conductive terminal and extending outward from the first side of the ceramic package structure along a third direction.

公开(公告)号：US20240021971A1

公开(公告)日：2024-01-18

申请号：US18353074

申请日：2023-07-15

Applicant: Texas Instruments Incorporated

Inventor： Aditya Nitin Jogalekar ,  Harshpreet Singh Phull Bakshi ,  Rajen Murugan ,  Sylvester Ankamah-Kusi

IPC: H01P5/107 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01Q1/22

CPC classification number: H01P5/107 ,  H01L23/66 ,  H05K1/024 ,  H05K1/112 ,  H05K3/4644 ,  H01Q1/2283 ,  H05K1/0243 ,  H01L2223/6633 ,  H05K2201/10098

Abstract: An example device includes: a multilayer build-up package substrate including trace conductor layers spaced from one another by dielectric material, and further including connection conductor layers coupling portions of the trace conductor layers through dielectric material, the multilayer build-up package substrate having a device side surface with one of the trace conductor layers and an opposing board side surface with one of the connection conductor layers; and a waveguide transition formed from the multilayer build-up package substrate, the waveguide transition having an input port formed from the connection conductor layer on the board side surface, and having at least two sub-transitions spaced laterally from one another, the at least two sub-transitions to couple a signal from the input port through the trace conductor layers and the connection conductor layers to a coplanar waveguide formed from the trace conductor layer on the device side surface.

公开(公告)号：US11621232B2

公开(公告)日：2023-04-04

申请号：US17246115

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

公开(公告)号：US20220352087A1

公开(公告)日：2022-11-03

申请号：US17246115

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.