公开(公告)号：US20230352850A1

公开(公告)日：2023-11-02

申请号：US18309720

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Murugan ,  Harshpreet Singh Phull Bakshi ,  Sylvester Ankamah-Kusi ,  Juan Herbsommer ,  Aditya Nitin Jogalekar

IPC: H01Q21/00 ,  H01Q1/22

CPC classification number: H01Q21/005 ,  H01Q1/2283

Abstract: An example microelectronic device package includes: a multilayer package substrate including a slotted waveguide antenna and having routing conductors, the multilayer package substrate having a device side surface and an opposing board side surface; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to slotted waveguide antenna by the routing conductors; and mold compound covering the semiconductor die, and a portion of the multilayer package substrate.

公开(公告)号：US20240178163A1

公开(公告)日：2024-05-30

申请号：US18072026

申请日：2022-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen M. Murugan ,  Aditya Nitin Jogalekar

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/06 ,  H01L23/31 ,  H01Q5/25 ,  H01Q9/28 ,  H01Q13/10

CPC classification number: H01L23/66 ,  H01L23/06 ,  H01L23/3107 ,  H01L24/20 ,  H01Q5/25 ,  H01Q9/285 ,  H01Q13/106 ,  H01L2223/6677 ,  H01L2224/221

Abstract: An example semiconductor package comprises a semiconductor die having a top surface, a passivation layer over the top surface, a first metal layer on the first passivation layer, an antenna formed in the first metal layer and offset from the semiconductor die, the antenna having a slot bow-tie configuration, a transmission line formed in the first metal layer, the transmission line coupling the semiconductor die to the antenna, and an insulating material separating the first metal layer from a second metal layer, the second metal layer configured to function as a ground reflector for the antenna. The second metal layer may extend below the antenna and the semiconductor die.

公开(公告)号：US20240213185A1

公开(公告)日：2024-06-27

申请号：US18146886

申请日：2022-12-27

Applicant: Texas Instruments Incorporated

Inventor： Aditya Nitin Jogalekar ,  Harshpreet Singh Phull Bakshi ,  Rajen Manicon Murugan ,  Sylvester Ankamah-Kusi

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01P3/00 ,  H01P3/12 ,  H01P5/107 ,  H01P11/00

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49838 ,  H01P3/003 ,  H01P3/121 ,  H01P5/107 ,  H01P11/002 ,  H01P11/003 ,  H01L2223/6633

Abstract: An electronic device includes a multilevel package substrate with a horizontal substrate integrated waveguide (SIW) with a channel, a vertical SIW with an opening, a grounded coplanar waveguide (GCPW), a first transition between the horizontal SIW and the GCPW, and a second transition between the horizontal and vertical SIWs, as well as a semiconductor die having conductive structures coupled to a signal trace and a ground trace of the GCPW, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate.

公开(公告)号：US20240021971A1

公开(公告)日：2024-01-18

申请号：US18353074

申请日：2023-07-15

Applicant: Texas Instruments Incorporated

Inventor： Aditya Nitin Jogalekar ,  Harshpreet Singh Phull Bakshi ,  Rajen Murugan ,  Sylvester Ankamah-Kusi

IPC: H01P5/107 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01Q1/22

CPC classification number: H01P5/107 ,  H01L23/66 ,  H05K1/024 ,  H05K1/112 ,  H05K3/4644 ,  H01Q1/2283 ,  H05K1/0243 ,  H01L2223/6633 ,  H05K2201/10098

Abstract: An example device includes: a multilayer build-up package substrate including trace conductor layers spaced from one another by dielectric material, and further including connection conductor layers coupling portions of the trace conductor layers through dielectric material, the multilayer build-up package substrate having a device side surface with one of the trace conductor layers and an opposing board side surface with one of the connection conductor layers; and a waveguide transition formed from the multilayer build-up package substrate, the waveguide transition having an input port formed from the connection conductor layer on the board side surface, and having at least two sub-transitions spaced laterally from one another, the at least two sub-transitions to couple a signal from the input port through the trace conductor layers and the connection conductor layers to a coplanar waveguide formed from the trace conductor layer on the device side surface.