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    Digital clock duty cycle correction
    11.
    发明授权
    Digital clock duty cycle correction 有权

    公开(公告)号：US10547297B2

    公开(公告)日：2020-01-28

    申请号：US16410508

    申请日：2019-05-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

    IPC: H03K3/017 ,  H03K5/156 ,  H02M3/07

    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

    Embedded clock in a communication system
    12.
    发明授权
    Embedded clock in a communication system 有权

    公开(公告)号：US10133297B2

    公开(公告)日：2018-11-20

    申请号：US15832882

    申请日：2017-12-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Floyd Payne

    IPC: H03M7/12 ,  G06F1/04 ,  H04B1/16 ,  H04B1/04 ,  H04L25/49

    Abstract: A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.

    Digital clock-duty-cycle correction
    13.
    发明授权
    Digital clock-duty-cycle correction 有权

    公开(公告)号：US10033365B2

    公开(公告)日：2018-07-24

    申请号：US15598339

    申请日：2017-05-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

    IPC: H03K3/017 ,  H03K5/156 ,  H02M3/07

    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

    Material detection and analysis using a dielectric waveguide
    14.
    发明授权
    Material detection and analysis using a dielectric waveguide 有权

    公开(公告)号：US10018576B2

    公开(公告)日：2018-07-10

    申请号：US14586842

    申请日：2014-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Juan Alejandro Herbsommer ,  Robert Floyd Payne

    IPC: G01V3/10 ,  G01N22/00

    CPC classification number: G01N22/00

    Abstract: A dielectric waveguide (DWG) may be used to identify a composition of a material that is in contact with the DWG. A radio frequency (RF) signal is transmitted into a dielectric waveguide located in contact with the material. The RF signal is received after it passes through the DWG. An insertion loss of the DWG is determined. The presence of the material may be inferred when the insertion loss exceeds a threshold value. The composition of the material may be inferred based on a correlation with the insertion loss. Alternatively, a volume of the material may be inferred based on a correlation with the insertion loss.

    Digital clock-duty-cycle correction
    15.
    发明授权
    Digital clock-duty-cycle correction 有权

    公开(公告)号：US09780768B2

    公开(公告)日：2017-10-03

    申请号：US14927949

    申请日：2015-10-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

    IPC: H03K5/04 ,  H03K5/156 ,  H02M3/07

    CPC classification number: H03K5/1565 ,  H02M3/07

    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

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