公开(公告)号：US20160190156A1

公开(公告)日：2016-06-30

申请号：US15066297

申请日：2016-03-10

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L21/28008 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/092 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect. A process of forming an integrated circuit containing elongated contacts, including elongated contacts which connect to at least three active areas and/or MOS gates, using exactly two contact photolithographic exposure operations, and including elongated contacts which connect to exactly two active areas and/or MOS gates and directly connect to a first level interconnect.

公开(公告)号：US20160190016A1

公开(公告)日：2016-06-30

申请号：US15059732

申请日：2016-03-03

Applicant: Texas Instruments Incorporated

Inventor： James Walter BLATCHFORD ,  Scott William JESSEN

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/762 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207

Abstract: A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

公开(公告)号：US20150325472A1

公开(公告)日：2015-11-12

申请号：US14803538

申请日：2015-07-20

Applicant: Texas Instruments Incorporated

Inventor： Thomas John ATON ,  Steven Lee PRINS ,  Scott William JESSEN

IPC: H01L21/768 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L21/32139 ,  G03F1/00 ,  G03F1/42 ,  G03F9/7084 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L29/6659 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.

Abstract translation: 在集成电路的制造期间将新图案对准多于一个先前定义的图案的方法。 一种将摄影图案掩模版与第一方向上的第一预定义图案对准并且还将光刻图案掩模版与第二方向上的第二预定义图案对准的方法。 将摄影图案掩模版与相同方向上的两个先前定义的图案对准的方法。