公开(公告)号：US20180018298A1

公开(公告)日：2018-01-18

申请号：US15714212

申请日：2017-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS DEUTSCHLAND GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US20170192751A1

公开(公告)日：2017-07-06

申请号：US14986349

申请日：2015-12-31

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Manish Goel

IPC: G06F7/523 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50 ,  G06F7/5324

Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

公开(公告)号：US20160292127A1

公开(公告)日：2016-10-06

申请号：US14678939

申请日：2015-04-04

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland, GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80

CPC classification number: G06F15/80 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/325 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3877

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract translation: 具有短并行指令字的低能量加速器处理器架构的方法和装置。 集成电路包括具有数据宽度N的系统总线，其中N是正整数; 耦合到所述系统总线并被配置为执行从耦合到所述系统总线的存储器检索的指令的中央处理器单元; 以及耦合到所述系统总线并被配置为执行从低能量加速器代码存储器检索的指令字的低能量加速器处理器，所述低能量加速器处理器具有多个执行单元，所述执行单元包括加载存储单元，负载系数单元，乘法 单元和蝶形/加法器ALU单元，每个执行单元被配置为响应于从检索到的指令字解码的操作码执行操作，其中指令字的宽度等于数据宽度N.附加方法和装置 被披露。

公开(公告)号：US20150127695A1

公开(公告)日：2015-05-07

申请号：US14072378

申请日：2013-11-05

Applicant: Texas Instruments Incorporated

Inventor： Kyong Ho Lee ,  Seok-Jun Lee ,  Manish Goel

IPC: G06F1/02

CPC classification number: G06F7/548

Abstract: A method for a processor computing a first trigonometric function to use an alternative trigonometric function for certain ranges of the operand. A modulo function may be used to provide an operand with a reduced range, and the modulo function may subtract in multiple steps in a manner that preserves low-order bits.

Abstract translation: 一种用于处理器计算第一三角函数以在操作数的某些范围使用替代三角函数的方法。 可以使用模函数来提供具有减小的范围的操作数，并且模函数可以以保持低位位的方式在多个步骤中减去。

公开(公告)号：US20150121043A1

公开(公告)日：2015-04-30

申请号：US14067343

申请日：2013-10-30

Applicant: Texas Instruments Incorporated

Inventor： Kyong Ho Lee ,  Seok-Jun Lee ,  Manish Goel

IPC: G06F9/30

CPC classification number: G06F17/17 ,  G06F7/483 ,  G06F7/544 ,  G06F9/3001

Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

Abstract translation: 公开了用于执行数学功能的计算机和方法。 计算机的实施例包括操作级别和驾驶员级别。 操作级别执行数学运算。 驾驶员级别包括第一查找表和第二查找表，其中第一查找表包括用于使用第一准确度来计算至少一个数学函数的第一数据。 第二查找表包括用于使用第二准确度计算至少一个数学函数的第二数据，其中第一准确度水平大于第二准确度。 驱动程序根据所选择的精度执行第一数据或第二数据。

公开(公告)号：US11341085B2

公开(公告)日：2022-05-24

申请号：US16920901

申请日：2020-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US10241791B2

公开(公告)日：2019-03-26

申请号：US15925957

申请日：2018-03-20

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F9/38

Abstract: An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor configured to execute instruction words received on the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers are coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

公开(公告)号：US09817791B2

公开(公告)日：2017-11-14

申请号：US14678939

申请日：2015-04-04

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland, GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F15/80 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/325 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3877

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US20160291974A1

公开(公告)日：2016-10-06

申请号：US14678944

申请日：2015-04-04

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland, GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F9/30 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F9/3013 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3877 ,  G06F9/3889 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus for a low energy accelerator processor architecture. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory ; a low energy accelerator processor configured to execute instruction words coupled to the system bus and having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

Abstract translation: 低能量加速器处理器架构的设备。 示例性布置是包括具有数据宽度N的系统总线的集成电路，其中N是正整数; 耦合到所述系统总线并被配置为执行从存储器检索的指令的中央处理器单元; 低能量加速器处理器，被配置为执行与所述系统总线耦合的指令字，并具有多个执行单元，所述多个执行单元包括加载存储单元，负载系数单元，乘法单元和蝶形/加法器ALU单元，每个执行单元 被配置为响应于检索到的指令字执行操作; 以及非正交数据寄存器文件，其包括耦合到所述多个执行单元的一组数据寄存器，所述寄存器耦合到所述多个执行单元中的所选择的执行单元。 公开了附加的方法和装置。