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    Memory pipeline control in a hierarchical memory system
    11.
    发明授权
    Memory pipeline control in a hierarchical memory system 有权

    公开(公告)号：US12197332B2

    公开(公告)日：2025-01-14

    申请号：US18584181

    申请日：2024-02-22

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/00 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0888

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS
    12.
    发明申请
    DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS 有权

    公开(公告)号：US20240403055A1

    公开(公告)日：2024-12-05

    申请号：US18800249

    申请日：2024-08-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Timothy Anderson

    IPC: G06F9/32 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/0897 ,  G06F13/16 ,  G06F13/40

    Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

    STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART
    16.
    发明申请
    STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART 审中-公开

    公开(公告)号：US20200272541A1

    公开(公告)日：2020-08-27

    申请号：US16808683

    申请日：2020-03-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Timothy Anderson

    IPC: G06F11/10 ,  G06F11/14 ,  G06F9/345 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/38 ,  G06F11/00

    Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
    18.
    发明申请
    MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM 有权

    公开(公告)号：US20250103502A1

    公开(公告)日：2025-03-27

    申请号：US18976474

    申请日：2024-12-11

    Applicant: Texas Instruments Incorporated

    Inventor： Abhijeet Ashok Chachad ,  Timothy Anderson ,  Kai Chirca ,  David Matthew Thompson

    IPC: G06F12/0842 ,  G06F1/14 ,  G06F9/38 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0888

    Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

    Streaming engine with short cut start instructions
    20.
    发明授权
    Streaming engine with short cut start instructions 有权

    公开(公告)号：US11983559B2

    公开(公告)日：2024-05-14

    申请号：US17508723

    申请日：2021-10-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy Anderson ,  Joseph Zbiciak

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/345 ,  G06F9/48 ,  G06F15/76

    CPC classification number: G06F9/485 ,  G06F9/30014 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/383 ,  G06F15/76

    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

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