公开(公告)号：US20070008863A1

公开(公告)日：2007-01-11

申请号：US11176740

申请日：2005-07-07

申请人： Corvin Liaw ,  Michael Kund ,  Gerhard Mueller

发明人： Corvin Liaw ,  Michael Kund ,  Gerhard Mueller

IPC分类号： G11B9/00

CPC分类号： G11B9/04 ,  B82Y10/00 ,  G11B9/1427 ,  G11B9/149

摘要： Embodiments of the present invention provide a method and memory device for storing and reading data. In one embodiment, the probe is positioned proximate to an area of a solid electrolyte layer in which the data is to be stored. A voltage difference is created across the solid electrolyte layer by applying a first voltage to a first side of the solid electrolyte layer via a tip of the probe and applying a second voltage to a second side of the solid electrolyte layer via an electrode layer coupled to the solid electrolyte layer. The voltage difference applied across the solid electrolyte layer causes ions from the electrode layer to be introduced into the solid electrolyte layer, creating a lowered resistance in the solid electrolyte layer. The lowered resistance corresponds to a first logical value stored in the solid electrolyte layer.

摘要翻译： 本发明的实施例提供一种用于存储和读取数据的方法和存储装置。 在一个实施例中，探针位于其中要存储数据的固体电解质层的区域附近。 通过经由探针的尖端向固体电解质层的第一侧施加第一电压，并通过耦合到固体电解质层的电极层向固体电解质层的第二侧施加第二电压，在固体电解质层上形成电压差 固体电解质层。 施加在固体电解质层两端的电压差使得来自电极层的离子被引入到固体电解质层中，导致固体电解质层中的电阻降低。 降低的电阻对应于存储在固体电解质层中的第一逻辑值。

公开(公告)号：US20060050547A1

公开(公告)日：2006-03-09

申请号：US11215443

申请日：2005-08-30

申请人： Corvin Liaw ,  Thomas Roehr ,  Michael Kund

发明人： Corvin Liaw ,  Thomas Roehr ,  Michael Kund

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0011 ,  G11C2213/78 ,  G11C2213/79

摘要： Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

公开(公告)号：US06661694B2

公开(公告)日：2003-12-09

申请号：US10000691

申请日：2001-11-15

申请人： Michael Kund ,  Reinhard Salchner

发明人： Michael Kund ,  Reinhard Salchner

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A configuration and a method for increasing the retention time and the storage security in a ferroelectric or ferromagnetic semiconductor memory utilize the imprint effect for increasing the remanent polarization or remanent magnetization of a material having a hysteresis property. The remanent polarization or magnetization is increased by writing a memory content a number of times to the same memory cells.

公开(公告)号：US07751163B2

公开(公告)日：2010-07-06

申请号：US11541402

申请日：2006-09-29

申请人： Alexander Duch ,  Ulrich Klostermann ,  Michael Kund

发明人： Alexander Duch ,  Ulrich Klostermann ,  Michael Kund

IPC分类号： H02H9/00

CPC分类号： H02H9/046 ,  G11C13/0011 ,  G11C13/0038 ,  G11C13/0059 ,  H02H9/02

摘要： An electric device protection circuit comprises at least one conductive bridging unit which electrically connects a terminal of the electric device to a protection node set to a protection potential, the protection potential being chosen such that the conductive bridging unit switches from a resistive state to a conductive state in case that the voltage or current at the terminal exceeds a predetermined threshold value.

摘要翻译： 电气设备保护电路包括至少一个导电桥接单元，其将电气设备的端子与设置为保护电位的保护节点电连接，所述保护电位被选择为使得导电桥接单元从电阻状态切换到导电 在端子处的电压或电流超过预定阈值的情况下状态。

公开(公告)号：US20090103350A1

公开(公告)日：2009-04-23

申请号：US11874768

申请日：2007-10-18

申请人： Michael Kund

发明人： Michael Kund

IPC分类号： G11C11/00 ,  G11C29/00 ,  H01L21/66

CPC分类号： G11C29/34 ,  G11C29/40 ,  G11C29/44 ,  G11C29/50008 ,  G11C29/70 ,  G11C2029/1208 ,  G11C2029/2602

摘要： According to one embodiment of the present invention, a method of testing a memory device including a memory cell array is provided, the method including: dividing the memory cell array into a plurality of memory cell array subunits, each memory cell array subunit including a plurality of resistivity changing memory cells; simultaneously testing all resistivity changing memory cells of a memory cell array subunit using a common testing signal; and repeating the testing for all further memory cell array subunits.

摘要翻译： 根据本发明的一个实施例，提供了一种测试包括存储单元阵列的存储器件的方法，所述方法包括：将存储单元阵列分成多个存储单元阵列子单元，每个存储单元阵列子单元包括多个 电阻率变化记忆细胞; 使用公共测试信号同时测试存储单元阵列子单元的所有电阻率变化的存储单元; 并重复对所有另外的存储单元阵列子单元的测试。

公开(公告)号：US07514362B2

公开(公告)日：2009-04-07

申请号：US11258367

申请日：2005-10-26

申请人： Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

发明人： Cay-Uwe Pinnow ,  Thomas Happ ,  Michael Kund ,  Gerhard Mueller

IPC分类号： H01L21/44

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76804 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

摘要翻译： 可以在图案化层中限定具有基本上小于可以光刻获得的特征尺寸的第一尺寸的开口的方法，包括将由不同于图案形成层的材料制成的牺牲层 图案化层上的预定层厚度。 之后，在牺牲层的表面上施加光致抗蚀剂层，并且在光致抗蚀剂层中光刻地限定具有第二尺寸的开口。 之后，以取决于牺牲层的层厚度以及第一和第二尺寸的方式设置蚀刻角度，并且以蚀刻角度设置蚀刻牺牲层。 之后，蚀刻图形层，去除牺牲层，并将填充材料引入图案化层中产生的开口中。

公开(公告)号：US20090073743A1

公开(公告)日：2009-03-19

申请号：US11856647

申请日：2007-09-17

申请人： Igor Kasko ,  Michael Kund

发明人： Igor Kasko ,  Michael Kund

IPC分类号： G11C11/24 ,  B05D5/12 ,  C21D9/00

CPC分类号： H01L45/1658 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146

摘要： A method of fabricating a memory cell including a solid electrolyte layer doped with metallic material and an electrode layer arranged above the solid electrolyte layer. The method includes doping a solid electrolyte layer with metallic material and forming an electrode layer above the solid electrolyte layer, wherein doping the solid electrolyte layer is carried out before forming the electrode layer.

摘要翻译： 一种制造包含掺杂有金属材料的固体电解质层和布置在固体电解质层上方的电极层的存储单元的方法。 该方法包括用金属材料掺杂固体电解质层并在固体电解质层上形成电极层，其中在形成电极层之前进行掺杂固体电解质层。

公开(公告)号：US20070018278A1

公开(公告)日：2007-01-25

申请号：US11189098

申请日：2005-07-25

申请人： Michael Kund ,  Josef Willer

发明人： Michael Kund ,  Josef Willer

IPC分类号： H01L29/00

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： The channel regions (T) of the memory cells are directed transversly to the word lines (2), which are arranged parallel at a distance from one another. Local interconnects (6) connect the source/drain regions of the memory cell transistors to bit lines running across the word lines and are connected to local interconnects in every next but one interspace between neighboring word lines. Every local interconnect is connected to only one source/drain region, which is enabled by enlarged shallow trench isolations (7) between the active areas. This memory cell array allows an individual programming and erasing of every single cell and can be integrated with a flash memory array comprising local interconnects and upper bit lines and is intended for file storage.

摘要翻译： 存储单元的通道区域（T）被横向地引导到彼此相隔一定距离并排布置的字线（2）。 本地互连（6）将存储单元晶体管的源极/漏极区域连接到跨过字线延伸的位线，并且在相邻字线之间的每个下一个但是一个间隔中连接到局部互连。 每个局部互连仅连接到一个源极/漏极区域，其通过在有源区域之间扩大的浅沟槽隔离（7）来实现。 该存储单元阵列允许单个单元的单独编程和擦除，并且可以与包括本地互连和高位线的闪存阵列集成，并且用于文件存储。

公开(公告)号：US07127650B2

公开(公告)日：2006-10-24

申请号：US10195598

申请日：2002-07-11

申请人： Abel Rios-Baez ,  Michael Kund

发明人： Abel Rios-Baez ,  Michael Kund

IPC分类号： G11C29/00

CPC分类号： G11C29/40

摘要： A test method for electronic memories includes reading out a previously defined test pattern sequentially as a time-dependent signal from the memory, determining the associated spectrum from the time-dependent signal by Fourier transformation, and assessing the memory to be tested using the spectrum. Also included is a suitable test device for the method.

公开(公告)号：US06674627B1

公开(公告)日：2004-01-06

申请号：US09705599

申请日：2000-11-03

申请人： Michael Kund

发明人： Michael Kund

IPC分类号： H01H4700

CPC分类号： G01R31/2887 ,  G01R3/00

摘要： A needle-card adjusting device for planarizing needle sets on a needle card, in which the needle card is connected to a circuit board used as a contact interface to a test head. The needle-card adjusting device has a separate, dynamically operating adjusting unit for adjusting the needle-card.

摘要翻译： 一种针卡调整装置，用于平针化针卡上的针组，其中针卡连接到用作与测试头的接触界面的电路板。 针卡调整装置具有用于调整针卡的单独的动态操作调节单元。