公开(公告)号：US11856745B2

公开(公告)日：2023-12-26

申请号：US17860977

申请日：2022-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H10B10/00 ,  G11C11/412 ,  H01L29/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768

CPC classification number: H10B10/12 ,  G11C11/412 ,  H01L21/76895 ,  H01L23/5226 ,  H01L27/0207 ,  H01L29/66477 ,  H10B10/18

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

公开(公告)号：US11043595B2

公开(公告)日：2021-06-22

申请号：US16441217

申请日：2019-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A semiconductor device includes a memory macro having first and second well pick-up (WPU) areas along first and second edges of the memory macro, respectively, and memory bit areas between the first and the second WPU areas. The first and second WPU areas are oriented lengthwise generally along a first direction. In each of the first and second WPU areas, the memory macro includes n-type wells and p-type wells arranged alternately along the first direction with a well boundary between each of the n-type wells and the adjacent p-type well. The memory macro further includes active regions; an isolation structure; gate structures, and a first dielectric layer that is disposed at each of the well boundaries. From a top view, the first dielectric layer extends generally along a second direction perpendicular to the first direction and through all the gate structures in the first and the second WPU areas.

公开(公告)号：US20200168616A1

公开(公告)日：2020-05-28

申请号：US16657421

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L27/11 ,  G06F17/50 ,  G11C11/412

Abstract: Well pick-up regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a circuit region; a first well pick-up (WPU) region; a first well oriented lengthwise along a first direction in the circuit region and extending into the first WPU region, the first well having a first conductivity type; and a second well oriented lengthwise along the first direction in the circuit region and extending into the first WPU region, the second well having a second conductivity type different from the first conductivity type, wherein the first well has a first portion in the circuit region and a second portion in the first WPU region, and the second portion of the first well has a width larger than the first portion of the first well along a second direction perpendicular to the first direction.

公开(公告)号：US10658242B2

公开(公告)日：2020-05-19

申请号：US16047121

申请日：2018-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chun Keng ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L21/311 ,  H01L21/3065

Abstract: A structure and a method of a semiconductor device structure are provided. The method includes forming a first fin structure, a second fin structure, and a third fin structure over a semiconductor substrate. The method includes forming first spacer elements over sidewalls of the first fin structure and the second fin structure and partially removing the first fin structure and the second fin structure. The method includes forming second spacer elements over sidewalls of the third fin structure and partially removing the third fin structure. The second spacer element is taller than the first spacer element. The method includes epitaxially growing a semiconductor material over the first fin structure, the second fin structure, and the third fin structure such that a merged semiconductor element is formed on the first fin structure and the second fin structure, and an isolated semiconductor element is formed on the third fin structure.

公开(公告)号：US20240237323A1

公开(公告)日：2024-07-11

申请号：US18444889

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC: H10B10/00 ,  G06F30/30 ,  G11C11/412

CPC classification number: H10B10/00 ,  G06F30/30 ,  G11C11/412

Abstract: Well pick-up (WPU) regions are disclosed herein for improving performance of memory arrays, such as static random access memory arrays. An exemplary semiconductor device includes a circuit region, a first WPU region, second WPU region, a first well of a first conductivity type, and a second well of a second conductivity type. The circuit region, the first WPU region, and the second WPU region are arranged along a first direction in sequence. The first well has a first portion disposed in the circuit region and a second portion disposed in the first WPU region. The second well has a first portion disposed in the circuit region, a second portion disposed in the first WPU region, and a third potion disposed in the second WPU region. Measured along the first direction a width of the first WPU region is less than a width of the second WPU region.

公开(公告)号：US20240222188A1

公开(公告)日：2024-07-04

申请号：US18609639

申请日：2024-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chang-Ta Yang

IPC: H01L21/762 ,  H01L21/3065 ,  H10B10/00

CPC classification number: H01L21/76224 ,  H01L21/3065 ,  H01L21/76232 ,  H10B10/12

Abstract: A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.

公开(公告)号：US11864368B2

公开(公告)日：2024-01-02

申请号：US17830967

申请日：2022-06-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jordan Hsu ,  Yu-Kuan Lin ,  Shau-Wei Lu ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Hung Lo

IPC: H10B10/00 ,  H01L27/092 ,  H10B99/00 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49

CPC classification number: H10B10/12 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/66803 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H10B99/00

Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.

公开(公告)号：US11641729B2

公开(公告)日：2023-05-02

申请号：US16721657

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jordan Hsu ,  Yu-Kuan Lin ,  Shau-Wei Lu ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Hung Lo

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L29/49 ,  H01L27/105

Abstract: A method for manufacturing a SRAM cell includes forming a first p-well in a semiconductor substrate; forming a first semiconductor fin extending within the first p-well; forming a first mask layer over the first semiconductor fin; patterning the first mask layer to expose a first channel region of the first semiconductor fin, while leaving a second channel region of the first semiconductor fin covered by the first mask layer; with the patterned first mask layer in place, doping the first channel region of the first semiconductor fin with a first dopant; after doping the first channel region of the first semiconductor fin, removing the first mask layer from the second channel region; and forming a first gate structure extending across the first channel region of the first semiconductor fin and a second gate structure extending across the second channel region of the first semiconductor fin.

公开(公告)号：US11621267B2

公开(公告)日：2023-04-04

申请号：US16854770

申请日：2020-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Yi Chao ,  Mei-Yun Wang

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/66 ,  H01L23/522 ,  H01L27/02 ,  H01L21/768

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

公开(公告)号：US11355499B2

公开(公告)日：2022-06-07

申请号：US16721632

申请日：2019-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jordan Hsu ,  Yu-Kuan Lin ,  Shau-Wei Lu ,  Chang-Ta Yang ,  Ping-Wei Wang ,  Kuo-Hung Lo

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49 ,  H01L27/105

Abstract: A static random access memory (SRAM) cell includes substrate, a first semiconductor fin, a first gate structure, a second semiconductor fin, and a second gate structure. The substrate has a first p-well and an n-well bordering the first p-well. The first semiconductor fin extends within the first p-well. The first gate structure extends across the first semiconductor fin and forms a first write-port pull-down transistor with the first semiconductor fin. The second semiconductor fin extends within the n-well. The second gate structure extends across the second semiconductor fin and forms a first write-port pull-up transistor with the second semiconductor fin. A channel region of the first write-port pull-down transistor has a higher doping concentration than a channel region of the first write-port pull-up transistor.