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公开(公告)号:US09281263B2
公开(公告)日:2016-03-08
申请号:US14258175
申请日:2014-04-22
发明人: Ming Han Lee , Hai-Ching Chen , Hsiang-Huan Lee , Tien-I Bao , Chi-Lin Teng
IPC分类号: H01L23/48 , H01L23/482 , H01L21/768 , H01L23/532 , H01L23/528
CPC分类号: H01L23/4827 , H01L21/76807 , H01L21/76834 , H01L21/76843 , H01L21/76852 , H01L21/76867 , H01L21/76885 , H01L21/76897 , H01L23/528 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要: Some embodiments of the present disclosure relate to an interconnect structure for connecting devices of a semiconductor substrate. The interconnect structure includes a dielectric layer over the substrate and a continuous conductive body passing through the dielectric layer. The continuous conductive body is made up of a lower body region and an upper body region. The lower body region has a first width defined between opposing lower sidewalls of the continuous conductive body, and the upper body region has a second width defined between opposing upper sidewalls of the continuous conductive body. The second width is less than the first width. A barrier layer separates the continuous conductive body from the dielectric layer.
摘要翻译: 本公开的一些实施例涉及用于连接半导体衬底的器件的互连结构。 所述互连结构包括在所述衬底上的电介质层和穿过所述电介质层的连续导电体。 连续导电体由下体区域和上体区域构成。 下体区域具有限定在连续导电体的相对的下侧壁之间的第一宽度,并且上体区域具有限定在连续导电体的相对的上侧壁之间的第二宽度。 第二宽度小于第一宽度。 阻挡层将连续导电体与电介质层分开。
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公开(公告)号:US20210376111A1
公开(公告)日:2021-12-02
申请号:US16888138
申请日:2020-05-29
发明人: Cheng-Chi Chuang , Lin-Yu Huang , Chia-Hao Chang , Yu-Ming Lin , Ting-Ya Lo , Chi-Lin Teng , Hsin-Yen Huang , Hai-Ching Chen
摘要: A method includes providing a structure having a gate stack; first gate spacers; a second gate spacer over one of the first gate spacers and having an upper portion over a lower portion; a dummy spacer; an etch stop layer; and a dummy cap. The method further includes removing the dummy cap, resulting in a first void above the gate stack and between the first gate spacers; removing the dummy spacer, resulting in a second void above the lower portion and between the etch stop layer and the upper portion; depositing a layer of a decomposable material into the first and the second voids; depositing a seal layer over the etch stop layer, the first and the second gate spacers, and the layer of the decomposable material; and removing the layer of the decomposable material, thereby reclaiming at least portions of the first and the second voids.
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公开(公告)号:US10211097B2
公开(公告)日:2019-02-19
申请号:US15063358
申请日:2016-03-07
发明人: Hsin-Yen Huang , Kai-Fang Cheng , Chi-Lin Teng , Shao-Kuan Lee , Hai-Ching Chen
IPC分类号: H01L21/768 , H01L23/532 , H01L23/522
摘要: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
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公开(公告)号:US09799603B2
公开(公告)日:2017-10-24
申请号:US15007779
申请日:2016-01-27
发明人: Kai-Fang Cheng , Chi-Lin Teng , Hai-Ching Chen , Hsin-Yen Huang , Tien-I Bao , Jung-Hsun Tsai
IPC分类号: H01L21/4763 , H01L23/528 , H01L21/768 , H01L23/522
CPC分类号: H01L23/5283 , H01L21/7681 , H01L21/76831 , H01L21/76877 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295
摘要: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a cover layer covering a first inner wall of the first opening. The cover layer has a second opening exposing the first conductive structure. The cover layer includes a metal oxide. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the cover layer. The second conductive structure is electrically connected to the first conductive structure.
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公开(公告)号:US20220246468A1
公开(公告)日:2022-08-04
申请号:US17728295
申请日:2022-04-25
发明人: Kai-Fang Cheng , Chi-Lin Teng , Hsin-Yen Huang , Hai-Ching Chen
IPC分类号: H01L21/768 , H01L21/02 , H01L21/311 , H01L21/3213
摘要: A semiconductor device includes a substrate, a first conductive feature disposed in a top portion of the substrate, a metal containing layer disposed on the first conductive feature, and a second conductive feature disposed on and through the metal containing layer and in physical contact with the first conductive feature. The metal containing layer includes an M-O—X group, M representing a metal atom, O representing an oxygen atom, and X representing an element other than hydrogen.
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公开(公告)号:US11355430B2
公开(公告)日:2022-06-07
申请号:US16885378
申请日:2020-05-28
发明人: Ting-Ya Lo , Chi-Lin Teng , Hai-Ching Chen , Hsin-Yen Huang , Shau-Lin Shue , Shao-Kuan Lee , Cheng-Chin Lee
IPC分类号: H01L23/522 , H01L23/538 , H01L21/768
摘要: Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.
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公开(公告)号:US11322395B2
公开(公告)日:2022-05-03
申请号:US16876432
申请日:2020-05-18
发明人: Hsin-Yen Huang , Chi-Lin Teng , Hai-Ching Chen , Shau-Lin Shue , Shao-Kuan Lee , Cheng-Chin Lee , Ting-Ya Lo
IPC分类号: H01L21/768 , H01L23/532 , H01L23/528
摘要: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.
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公开(公告)号:US11315828B2
公开(公告)日:2022-04-26
申请号:US16451432
申请日:2019-06-25
发明人: Kai-Fang Cheng , Chi-Lin Teng , Hsin-Yen Huang , Hai-Ching Chen
IPC分类号: H01L21/768 , H01L21/02 , H01L21/336 , H01L21/311 , H01L21/3213
摘要: A method includes providing a dielectric layer; forming a metal line in the dielectric layer; forming an etch stop layer on the metal line, wherein the etch stop layer includes a metal atom bonded with a hydroxyl group; performing a treatment process to the etch stop layer to displace hydrogen in the hydroxyl group with an element other than hydrogen; partially etching the etch stop layer to expose the metal line; and forming a conductive feature above the etch stop layer and in physical contact with the metal line.
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公开(公告)号:US11538749B2
公开(公告)日:2022-12-27
申请号:US17097505
申请日:2020-11-13
发明人: Shao-Kuan Lee , Hsin-Yen Huang , Cheng-Chin Lee , Kuang-Wei Yang , Ting-Ya Lo , Chi-Lin Teng , Hsiao-Kang Chang , Shau-Lin Shue
IPC分类号: H01L23/522 , H01L21/768 , H01L23/532
摘要: The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.
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公开(公告)号:US20210193566A1
公开(公告)日:2021-06-24
申请号:US16885378
申请日:2020-05-28
发明人: Ting-Ya Lo , Chi-Lin Teng , Hai-Ching Chen , Hsin-Yen Huang , Shau-Lin Shue , Shao-Kuan Lee , Cheng-Chin Lee
IPC分类号: H01L23/522 , H01L23/538 , H01L21/768
摘要: Some embodiments relate to a semiconductor structure including an inter-level dielectric (ILD) layer overlying a substrate. A conductive via is disposed within the ILD layer. A plurality of conductive wires overlie the ILD layer. The plurality of conductive wires includes a first conductive wire laterally offset a second conductive wire. A dielectric structure is disposed laterally between the first and second conductive wires. The dielectric structure includes a first dielectric liner, a dielectric layer, and an air-gap. The air-gap is disposed between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is disposed along an upper surface of the dielectric structure. The dielectric capping layer continuously extends between opposing sidewalls of the dielectric structure and is laterally offset from the plurality of conductive wires.
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