公开(公告)号：US10109736B2

公开(公告)日：2018-10-23

申请号：US14620399

申请日：2015-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Po-Chun Liu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/15 ,  H01L29/205 ,  H01L21/02 ,  H01L29/66

Abstract: A transistor with a multi-strained layer superlattice (SLS) structure is provided. A first strained layer superlattice (SLS) layer is arranged over a substrate. A first buffer layer is arranged over the first SLS layer and includes dopants configured to increase a resistance of the first buffer layer. A second SLS layer is arranged over the first buffer layer. A second buffer layer is arranged over the second SLS layer and includes dopants configured to increase a resistance of the second buffer layer. A channel layer is arranged over the second buffer layer. An active layer is arranged over and directly abuts the channel layer. The channel and active layers collectively define a heterojunction. A method for manufacturing the transistor is also provided.

公开(公告)号：US20210336006A1

公开(公告)日：2021-10-28

申请号：US17064811

申请日：2020-10-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/08 ,  H01L27/12 ,  H01L29/167 ,  H01L27/088 ,  H01L21/84 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.

公开(公告)号：US10109729B2

公开(公告)日：2018-10-23

申请号：US15242653

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/338 ,  H01L29/778 ,  H01L29/43 ,  H01L29/20 ,  H01L29/205 ,  H01L29/201

Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.

公开(公告)号：US20170271473A1

公开(公告)日：2017-09-21

申请号：US15613660

申请日：2017-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L23/29 ,  H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L23/31

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

公开(公告)号：US20160359034A1

公开(公告)日：2016-12-08

申请号：US15242653

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.

Abstract translation: 本公开涉及具有施主双层的晶体管器件，其被配置为在源极和漏极触点内提供低电阻，同时保持沟道层内的高迁移率二维电子气以及相关的形成方法。 在一些实施例中，晶体管器件具有设置在衬底上的沟道层和设置在沟道层上的施主双层。 施主双层包括设置在沟道层上并具有第一范围内的第一摩尔分数z的AlzGa（1-z）N的迁移率增强层，以及Al x Ga（1-x）N的电阻减小层 设置在AlzGa（1-z）N的迁移率增强层上并与之接触，并且在小于第一范围的第二范围内具有第二摩尔分数x。 源极和漏极接触在Al x Ga（1-x）N的电阻减少层之上。 供体双层具有从施主双层的顶表面到底表面单调减小的导带能量。

公开(公告)号：US20160351684A1

公开(公告)日：2016-12-01

申请号：US15234590

申请日：2016-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L23/29

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract translation: 本公开的一些实施例涉及一种高电子迁移率晶体管（HEMT），其包括布置在半导体衬底上的异质结结构。 异质结结构包括由作为e-HEMT的沟道区域的第一III族氮化物材料制成的二元III / V半导体层和布置在二元III / V半导体层上的三元III / V半导体层，并制成 的第二III族氮化物材料作为阻挡层。 源极和漏极区域布置在三元III / V半导体层上方并且彼此横向间隔开。 栅极结构布置在异质结结构之上并且布置在源区和漏区之间。 栅极结构由第三III族氮化物材料制成。 第一钝化层围绕栅极结构的侧壁设置并由第四III族氮化物材料制成。

公开(公告)号：US09425301B2

公开(公告)日：2016-08-23

申请号：US14488380

申请日：2014-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205 ,  H01L23/29 ,  H01L29/10

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract translation: 本公开的一些实施例涉及一种高电子迁移率晶体管（HEMT），其包括布置在半导体衬底上的异质结结构。 异质结结构包括由作为e-HEMT的沟道区域的第一III族氮化物材料制成的二元III / V半导体层和布置在二元III / V半导体层上的三元III / V半导体层，并制成 的第二III族氮化物材料作为阻挡层。 源极和漏极区域布置在三元III / V半导体层上方并且彼此横向间隔开。 栅极结构布置在异质结结构之上并且布置在源区和漏区之间。 栅极结构由第三III族氮化物材料制成。 第一钝化层围绕栅极结构的侧壁设置并由第四III族氮化物材料制成。

公开(公告)号：US09425276B2

公开(公告)日：2016-08-23

申请号：US13745925

申请日：2013-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

IPC: H01L29/15 ,  H01L31/0256 ,  H01L29/66 ,  H01L21/338 ,  H01L29/43 ,  H01L29/778 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

Abstract translation: 本公开涉及双层AlGaN的施主层和在高电子迁移率晶体管（HEMT）内的相关制造方法，其被配置为提供低电阻欧姆源极和漏极触点以降低功耗，同时保持高的迁移率 在HEMT的通道内的二维电子气（2DEG）。 双层AlGaN的施主层包括位于迁移率增强层上的Al x Ga（1-x）N的电阻减小层AlzGa（1-z）N的迁移率增强层，其中欧姆源和漏极 触点连接到HEMT。 移动性增强层下方设置沟道层，其中2DEG驻留，形成HEMT的沟道。

公开(公告)号：US20150318387A1

公开(公告)日：2015-11-05

申请号：US14488380

申请日：2014-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Chin Chiu ,  Chi-Ming Chen ,  Cheng-Yuan Tsai ,  Fu-Wei Yao

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/66462 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/0254 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

Abstract translation: 本公开的一些实施例涉及一种高电子迁移率晶体管（HEMT），其包括布置在半导体衬底上的异质结结构。 异质结结构包括由作为e-HEMT的沟道区域的第一III族氮化物材料制成的二元III / V半导体层和布置在二元III / V半导体层上的三元III / V半导体层，并制成 的第二III族氮化物材料作为阻挡层。 源极和漏极区域布置在三元III / V半导体层上方并且彼此横向间隔开。 栅极结构布置在异质结结构之上并且布置在源区和漏区之间。 栅极结构由第三III族氮化物材料制成。 第一钝化层围绕栅极结构的侧壁设置并由第四III族氮化物材料制成。

公开(公告)号：US20140203289A1

公开(公告)日：2014-07-24

申请号：US13745925

申请日：2013-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7783

Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

Abstract translation: 本公开涉及双层AlGaN的施主层和在高电子迁移率晶体管（HEMT）内的相关制造方法，其被配置为提供低电阻欧姆源极和漏极触点以降低功耗，同时保持高的迁移率 在HEMT的通道内的二维电子气（2DEG）。 双层AlGaN的施主层包括位于迁移率增强层上的Al x Ga（1-x）N的电阻减小层AlzGa（1-z）N的迁移率增强层，其中欧姆源和漏极 触点连接到HEMT。 移动性增强层下方设置沟道层，其中2DEG驻留，形成HEMT的沟道。