公开(公告)号：US09236445B2

公开(公告)日：2016-01-12

申请号：US14156505

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wen Liu ,  Tsung-Hsing Yu ,  Wei-Hao Wu ,  Meikei Ieong ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/36

CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.

Abstract translation: 本公开提供了一种形成晶体管的方法。 在该方法中，在半导体衬底上形成虚拟栅极结构。 然后在半导体衬底中形成源极/漏极区，使得布置在半导体衬底中的伪栅极结构下方的沟道区彼此分离源极/漏极。 在形成源极/漏极区之后，去除伪栅极结构。 在虚拟栅极结构被去除之后，去除沟道区域的表面区域以形成沟道区域凹陷。 然后在沟道区域凹陷中外延生长替换沟道区。

公开(公告)号：US20150200296A1

公开(公告)日：2015-07-16

申请号：US14156515

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Yeh Hsu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/16 ,  H01L21/02 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7836 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.

Abstract translation: 本公开涉及一种形成具有提供电压阈值的低变化的碳注入区域的晶体管器件的方法和相关联的器件。 该方法通过在半导体衬底内形成阱区进行。 选择性地蚀刻半导体衬底以在阱区内形成凹陷。 在形成凹部之后，选择性地进行碳注入，以在凹部下方的位置在半导体衬底内形成碳注入区域。 然后进行外延生长以在覆盖碳注入区域的位置处在凹槽内形成一个或多个外延层。 源极和漏极区域随后形成在半导体衬底内，使得包括一个或多个外延层的沟道区域将源极/漏极彼此分离。

公开(公告)号：US09768297B2

公开(公告)日：2017-09-19

申请号：US14935760

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Yeh Hsu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L21/02 ,  H01L29/08 ,  H01L29/16 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/7836 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

公开(公告)号：US09660049B2

公开(公告)日：2017-05-23

申请号：US14672298

申请日：2015-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Ken-Ichi Goto

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L29/08 ,  H01L21/265 ,  H01L29/51

CPC classification number: H01L29/66492 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833 ,  Y10S438/931

Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.

公开(公告)号：US09653545B2

公开(公告)日：2017-05-16

申请号：US14661237

申请日：2015-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mahaveer Sathaiya Dhanyakumar ,  Wei-Hao Wu ,  Tsung-Hsing Yu ,  Chia-Wen Liu ,  Tzer-Min Shen ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265

CPC classification number: H01L29/0653 ,  H01L21/26586 ,  H01L21/76232 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

公开(公告)号：US20150263096A1

公开(公告)日：2015-09-17

申请号：US14208353

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Ken-Ichi Goto ,  Chia-Wen Liu ,  Yeh Hsu

IPC: H01L29/165 ,  H01L29/10 ,  H01L29/16 ,  H01L29/778 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02535 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

Abstract: Some embodiments of the present disclosure relate to an epitaxially grown replacement channel region within a transistor, which mitigates the variations within the channel of the transistor due to fluctuations in the manufacturing processes. The replacement channel region is formed by recessing source/drain and channel regions of the semiconductor substrate, and epitaxially growing a replacement channel region within the recess, which comprises epitaxially growing a lower epitaxial channel region over a bottom surface of the recess, and epitaxially growing an upper epitaxial channel region over a bottom surface of the recess. The lower epitaxial channel region retards dopant back diffusion from the upper epitaxial channel region, resulting in a steep retrograde dopant profile within the replacement channel region. The upper epitaxial channel region increases carrier mobility within the channel. The replacement channel region provides improved drive current, thereby enabling better performance and higher yield.

Abstract translation: 本公开的一些实施例涉及晶体管内的外延生长的替换沟道区，其由于制造工艺的波动而减轻晶体管的沟道内的变化。 替换通道区域通过使半导体衬底的源极/漏极和沟道区域凹陷形成，并且在凹槽内外延生长置换沟道区域，其包括在凹部的底表面上外延生长下部外延沟道区域，并且外延生长 在所述凹部的底表面上方的上部外延沟道区域。 下部外延沟道区域从上部外延沟道区域延迟掺杂剂反向扩散，导致替代沟道区域内的陡峭的逆向掺杂物分布。 上部外延沟道区增加了沟道内的载流子迁移率。 替代通道区域提供改善的驱动电流，从而实现更好的性能和更高的产量。

公开(公告)号：US20150200272A1

公开(公告)日：2015-07-16

申请号：US14156505

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Wen Liu ,  Tsung-Hsing Yu ,  Wei-Hao Wu ,  Meikei Ieong ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/36

CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.

Abstract translation: 本公开提供了一种形成晶体管的方法。 在该方法中，在半导体衬底上形成虚拟栅极结构。 然后在半导体衬底中形成源极/漏极区，使得布置在半导体衬底中的伪栅极结构下方的沟道区彼此分离源极/漏极。 在形成源极/漏极区之后，去除伪栅极结构。 在虚拟栅极结构被去除之后，去除沟道区域的表面区域以形成沟道区域凹陷。 然后在沟道区域凹陷中外延生长替换沟道区。