公开(公告)号：US11342242B2

公开(公告)日：2022-05-24

申请号：US16798431

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Jung Wu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Sheng-Tsung Hsiao ,  Jen-Yu Wang

IPC: H01L23/46 ,  H01L21/52 ,  H01L23/40 ,  H01L23/498 ,  H01L23/473 ,  H01L23/42

Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.

公开(公告)号：US11315900B2

公开(公告)日：2022-04-26

申请号：US16983178

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tung-Liang Shao ,  Chih-Hang Tung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/075

Abstract: A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.

公开(公告)号：US11056459B2

公开(公告)日：2021-07-06

申请号：US16373900

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hang Tung ,  Tung-Liang Shao ,  Su-Chun Yang ,  Geng-Ming Chang ,  Chen-Hua Yu

IPC: H01L23/00

Abstract: A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated.

公开(公告)号：US20210050251A1

公开(公告)日：2021-02-18

申请号：US16866565

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Li Hsiao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang

IPC: H01L21/768 ,  H01L21/50

Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.

公开(公告)号：US11996383B2

公开(公告)日：2024-05-28

申请号：US17728024

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tung-Liang Shao ,  Chih-Hang Tung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/075

CPC classification number: H01L24/73 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/0756 ,  H01L2224/73253

Abstract: A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.

公开(公告)号：US11996351B2

公开(公告)日：2024-05-28

申请号：US17841007

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Tsung Hsiao ,  Jen Yu Wang ,  Chung-Jung Wu ,  Tung-Liang Shao ,  Chih-Hang Tung

IPC: H01L23/473 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/58

CPC classification number: H01L23/473 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/585 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.

公开(公告)号：US11581281B2

公开(公告)日：2023-02-14

申请号：US17232528

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Chih-Hang Tung

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

公开(公告)号：US11515233B2

公开(公告)日：2022-11-29

申请号：US16869594

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang Shao ,  Lawrence Chiang Sheu ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Yi-Li Hsiao

IPC: H01L23/473 ,  H01L23/467

Abstract: An apparatus includes a semiconductor component and a cooling structure. The cooling structure is over a back side of the semiconductor component. The cooling structure includes a housing, a liquid delivery device and a gas exhaust device. The housing includes a cooling space adjacent to the semiconductor component. The liquid delivery device is connected to an inlet of the housing and is configured to deliver a liquid coolant into the cooling space from the inlet. The gas exhaust device is connected to an outlet of the housing and is configured to lower a pressure in the housing.

公开(公告)号：US11443981B2

公开(公告)日：2022-09-13

申请号：US16866565

申请日：2020-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Li Hsiao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Tung-Liang Shao ,  Su-Chun Yang

IPC: H01L21/768 ,  H01L21/50 ,  H01L21/60

Abstract: A bonding method of package components and a bonding apparatus are provided. The method includes: providing at least one first package component and a second package component, wherein the at least one first package component has first electrical connectors and a first dielectric layer at a bonding surface of the at least one first package component, and the second package component has second electrical connectors and a second dielectric layer at a bonding surface of the second package component; bringing the at least one first package component and the second package component in contact, such that the first electrical connectors approximate or contact the second electrical connectors; and selectively heating the first electrical connectors and the second electrical connectors by electromagnetic induction, in order to bond the first electrical connectors with the second electrical connectors.

公开(公告)号：US20220246574A1

公开(公告)日：2022-08-04

申请号：US17728024

申请日：2022-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Tung-Liang Shao ,  Chih-Hang Tung

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/075

Abstract: A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.