公开(公告)号：US20190131222A1

公开(公告)日：2019-05-02

申请号：US16222118

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/498 ,  H01L23/433 ,  H01L21/48 ,  H01L23/373

Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.

公开(公告)号：US10276471B2

公开(公告)日：2019-04-30

申请号：US15855305

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L23/48 ,  H01L21/50 ,  H01L31/0232 ,  H01L31/09 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L31/0203 ,  H01L33/52 ,  H01L33/48 ,  H01L23/28 ,  H01L23/485 ,  H01L23/00 ,  H01L27/146 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/29 ,  H01L25/16 ,  H01L25/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.

公开(公告)号：US10177082B2

公开(公告)日：2019-01-08

申请号：US15823786

申请日：2017-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/373 ,  H01L23/433 ,  H01L23/31

Abstract: A method of forming a semiconductor package includes growing a layer of carbon nano material on a chip. The chip has a first surface and a second surface and the layer of carbon nano material is grown on the first surface of the chip. The layer of carbon nano material is configured to provide a path through which heat generated from the chip is dissipated. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the layer of carbon nano material.

公开(公告)号：US20180090425A1

公开(公告)日：2018-03-29

申请号：US15823786

申请日：2017-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/498 ,  H01L23/373 ,  H01L21/48 ,  H01L23/433 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L21/4871 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/373 ,  H01L23/4334 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A method of forming a semiconductor package includes growing a layer of carbon nano material on a chip. The chip has a first surface and a second surface and the layer of carbon nano material is grown on the first surface of the chip. The layer of carbon nano material is configured to provide a path through which heat generated from the chip is dissipated. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the layer of carbon nano material.

公开(公告)号：US09568677B2

公开(公告)日：2017-02-14

申请号：US13905404

申请日：2013-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/136 ,  G02B6/43 ,  G02B6/12

CPC classification number: G02B6/136 ,  G02B6/12004 ,  G02B6/43

Abstract: Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface.

Abstract translation: 提供形成波导结构的实施例。 波导结构包括基板，并且基板具有互连区域和波导区域。 波导结构还包括形成在衬底中的沟槽，并且沟槽具有倾斜的侧壁表面和基本平坦的底部。 波导结构还包括形成在基板上的底部包层，并且底部包层从互连区域延伸到波导区域，并且底部包层用作互连区域中的绝缘层。 波导结构还包括形成在倾斜侧壁表面上的底部包层上的金属层。

公开(公告)号：US11658044B2

公开(公告)日：2023-05-23

申请号：US17205146

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/4871 ,  H01L21/4878 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/3737 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/2919 ,  H01L2924/00014 ,  H01L2224/83101 ,  H01L2924/00014

Abstract: A semiconductor package includes a wafer and at least one chip attached on first portions of an upper surface of the wafer. Further, the semiconductor package includes an insulating barrier layer, a thermally conductive layer, and a heat sink. The insulating barrier layer is arranged over the at least one chip attached on first portions of an upper surface of the wafer. The thermally conductive layer is arranged over the insulating barrier layer and at least partially encapsulates the at least one chip. The heat sink is arranged over the thermally conductive layer.

公开(公告)号：US11088058B2

公开(公告)日：2021-08-10

申请号：US16600752

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/373 ,  H01L23/498 ,  H01L23/433 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.

公开(公告)号：US10983278B2

公开(公告)日：2021-04-20

申请号：US16141621

申请日：2018-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kai-Fang Cheng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/132 ,  H01L21/56 ,  H01L29/06 ,  H01L23/31 ,  G02B6/138 ,  G02B6/122 ,  G02B6/136 ,  H01L21/48 ,  G02B6/12

Abstract: An apparatus comprises a substrate having a plateau region and a trench region, a metal layer over the plateau region, a semiconductor component over the trench region, wherein a gap is between the plateau region and the semiconductor component, an adhesion promoter layer over the plateau region, the semiconductor component and the gap, a dielectric layer over the adhesion promoter layer and a bonding interface formed between the adhesion promoter layer and the dielectric layer, wherein the bonding interface comprises a chemical structure comprising a first dielectric material of the adhesion promoter layer and a second dielectric material of the dielectric layer.

公开(公告)号：US10861817B2

公开(公告)日：2020-12-08

申请号：US16666708

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/373 ,  H01L21/56 ,  H01L23/31 ,  H01L23/433

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip attached to a first substrate and a thermal conductivity layer attached to the first chip. A molding compound encapsulates the chip and the thermal conductivity layer. Electrical connectors are arranged between the first substrate and a board. The molding compound covers upper surfaces of the thermal conductivity layer facing away from the electrical connectors.

公开(公告)号：US20200066671A1

公开(公告)日：2020-02-27

申请号：US16666708

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/42 ,  H01L21/56

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip attached to a first substrate and a thermal conductivity layer attached to the first chip. A molding compound encapsulates the chip and the thermal conductivity layer. Electrical connectors are arranged between the first substrate and a board. The molding compound covers upper surfaces of the thermal conductivity layer facing away from the electrical connectors.