公开(公告)号：US20210305409A1

公开(公告)日：2021-09-30

申请号：US17333676

申请日：2021-05-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Li-Te LIN ,  Chung-Cheng WU ,  Gwan-Sin CHANG ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/49 ,  H01L29/40

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

公开(公告)号：US20170154978A1

公开(公告)日：2017-06-01

申请号：US14954208

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu YEH ,  Chung-Cheng WU ,  Cheng-Long CHEN ,  Gwan-Sin CHANG ,  Pang-Yen TSAI ,  Yen-Ming CHEN ,  Yasutoshi OKUNO ,  Ying-Hsuan WANG

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/165 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/3081 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.

公开(公告)号：US20250089332A1

公开(公告)日：2025-03-13

申请号：US18962707

申请日：2024-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Li-Te LIN ,  Chung-Cheng WU ,  Gwan-Sin CHANG ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

公开(公告)号：US20190131274A1

公开(公告)日：2019-05-02

申请号：US15794286

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Chun-Fu CHENG ,  Chung-Cheng WU ,  Yi-Han WANG ,  Chia-Wen LIU

IPC: H01L25/065 ,  H01L25/04 ,  H01L21/02

Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.

公开(公告)号：US20180145176A1

公开(公告)日：2018-05-24

申请号：US15355844

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7851 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed having a gate dielectric and a gate electrode in the opening. A dielectric material is formed abutting the portion of the gate structure.