公开(公告)号：US20170110578A1

公开(公告)日：2017-04-20

申请号：US14883452

申请日：2015-10-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi OKUNO ,  Cheng-Long CHEN ,  Meng-Chun CHANG ,  Sung-Li WANG ,  Yi-Fang PAI ,  Yusuke ONIKI

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/768 ,  H01L29/165 ,  H01L29/04 ,  H01L23/535 ,  H01L29/66 ,  H01L29/24

CPC classification number: H01L29/7848 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/535 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.

公开(公告)号：US20180277538A1

公开(公告)日：2018-09-27

申请号：US15990271

申请日：2018-05-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao CHANG ,  Ming-Shan SHIEH ,  Cheng-Long CHEN ,  Wai-Yi LIEN ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/78 ,  H01L29/45 ,  H01L29/423 ,  H01L29/417 ,  H01L23/485 ,  H01L21/768

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L29/0676 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a transistor over a substrate, wherein the transistor includes a source, a drain over the source, a semiconductor channel between the source and the drain, and a gate surrounding the semiconductor channel. A silicide layer is formed over the drain of the transistor. A capping layer is formed over the silicide layer. Portions of the capping layer and the silicide layer are removed to define a drain pad over the drain of the transistor.

公开(公告)号：US20200058560A1

公开(公告)日：2020-02-20

申请号：US16535701

申请日：2019-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Long CHEN ,  Yasutoshi OKUNO ,  Pang-Yen TSAI

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L29/167 ,  H01L29/08

Abstract: A method for forming an epitaxial source/drain structure in a semiconductor device includes providing a substrate having a plurality of fins extending from the substrate. In some embodiments, a liner layer is formed over the plurality of fins. The liner layer is patterned to expose a first group of fins of the plurality of fins in a first region. In some embodiments, a first epitaxial layer is formed over the exposed first group of fins and a barrier layer is formed over the first epitaxial layer. Thereafter, the patterned liner layer may be removed. In various examples, a second epitaxial layer is selectively formed over a second group of fins of the plurality of fins in a second region.

公开(公告)号：US20160049397A1

公开(公告)日：2016-02-18

申请号：US14461061

申请日：2014-08-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hao CHANG ,  Ming-Shan SHIEH ,  Cheng-Long CHEN ,  Wai-Yi LIEN ,  Chih-Hao WANG

IPC: H01L27/092 ,  H01L29/45 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/285 ,  H01L21/768 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L29/0676 ,  H01L29/41741 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/7827 ,  H01L29/78642 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source electrode, at least one semiconductor channel, a gate electrode, a drain electrode, and a drain pad. The source electrode is disposed in a substrate. The semiconductor channel extends substantially perpendicular to the source electrode. The gate electrode surrounds the semiconductor channel. The drain electrode is disposed on top of the semiconductor channel. The drain pad is disposed on the drain electrode, wherein the drain pad comprises multiple conductive layers.

Abstract translation: 提供了晶体管，集成电路和制造集成电路的方法。 在各种实施例中，晶体管包括源电极，至少一个半导体沟道，栅电极，漏电极和漏极焊盘。 源电极设置在基板中。 半导体通道基本上垂直于源电极延伸。 栅电极围绕半导体通道。 漏电极设置在半导体通道的顶部。 漏极焊盘设置在漏极电极上，其中漏极焊盘包括多个导电层。

公开(公告)号：US20210313236A1

公开(公告)日：2021-10-07

申请号：US17347281

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Long CHEN ,  Yasutoshi OKUNO ,  Pang-Yen TSAI

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/08 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L29/167

Abstract: A method for forming an epitaxial source/drain structure in a semiconductor device includes providing a substrate having a plurality of fins extending from the substrate. In some embodiments, a liner layer is formed over the plurality of fins. The liner layer is patterned to expose a first group of fins of the plurality of fins in a first region. In some embodiments, a first epitaxial layer is formed over the exposed first group of fins and a barrier layer is formed over the first epitaxial layer. Thereafter, the patterned liner layer may be removed. In various examples, a second epitaxial layer is selectively formed over a second group of fins of the plurality of fins in a second region.

公开(公告)号：US20170154978A1

公开(公告)日：2017-06-01

申请号：US14954208

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu YEH ,  Chung-Cheng WU ,  Cheng-Long CHEN ,  Gwan-Sin CHANG ,  Pang-Yen TSAI ,  Yen-Ming CHEN ,  Yasutoshi OKUNO ,  Ying-Hsuan WANG

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/165 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3065 ,  H01L21/3081 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.