公开(公告)号：US09852989B1

公开(公告)日：2017-12-26

申请号：US15397036

申请日：2017-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen Lin ,  Min-Yuan Tsai ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5226

Abstract: Power grids of an IC are provided. A power grid includes first power traces disposed in a first metal layer and parallel to a first direction, second power traces disposed in a second metal layer and parallel to a second direction that is perpendicular to the first direction, and third power traces disposed in the first metal layer parallel to the first direction. The first power traces arranged in the same straight line are separated from each other by a plurality of first gaps. The third power traces arranged in the same straight line are separated from each other by a plurality of second gaps. Each first gap is surrounded by the two adjacent third power traces. Each second gap is surrounded by the two adjacent first power traces. The first power traces are coupled to the third power traces via the second power traces.

公开(公告)号：US20150091543A1

公开(公告)日：2015-04-02

申请号：US14296042

申请日：2014-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jerry Chang-Jui KAO ,  Chien-Ju Chao ,  Chin-Shen Lin ,  Nitesh Katta ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H03K17/56

CPC classification number: H03K19/0013 ,  H02M3/155 ,  H02M3/156 ,  H02M3/157 ,  H02M2001/0012

Abstract: A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data.

Abstract translation: 公开了包括多个电压控制电路和控制模块的电路。 每个电压控制电路由控制信号控制。 控制模块被配置为产生控制信号并且根据电压控制电路的当前处理转角条件和第一预定数据和第二预定数据中的至少一个来确定控制信号的电压电平或脉冲宽度。

公开(公告)号：US12131109B2

公开(公告)日：2024-10-29

申请号：US18513349

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/30 ,  G06F30/39 ,  G06F30/392 ,  G06F30/394 ,  G06F30/396 ,  G06F30/398 ,  G06F119/06 ,  G06F119/12

CPC classification number: G06F30/392 ,  G06F30/39 ,  G06F30/394 ,  G06F30/396 ,  G06F30/398 ,  G06F2119/06 ,  G06F2119/12

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US12008302B2

公开(公告)日：2024-06-11

申请号：US18173731

申请日：2023-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung Chang ,  Yuan-Te Hou ,  Chung-Hsing Wang ,  Yung-Chin Hou

IPC: H01L23/528 ,  G06F30/20 ,  G06F30/327 ,  G06F30/337 ,  G06F30/373 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/00 ,  H01L27/088

CPC classification number: G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  G06F30/394 ,  H01L23/528 ,  H01L27/0886 ,  G06F30/337 ,  G06F30/373 ,  G06F30/398

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.

公开(公告)号：US11908853B2

公开(公告)日：2024-02-20

申请号：US18069887

申请日：2022-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan Chang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Sheng-Fong Chen ,  Po-Hsiang Huang ,  Hiranmay Biswas ,  Sheng-Hsiung Chen ,  Aftab Alam Khan

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

CPC classification number: H01L27/0207 ,  G06F30/394 ,  H01L23/5226 ,  H01L27/11807 ,  H01L2027/11881

Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.

公开(公告)号：US11853678B2

公开(公告)日：2023-12-26

申请号：US18096906

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/39 ,  G06F30/398 ,  G06F119/06 ,  G06F119/12

CPC classification number: G06F30/392 ,  G06F30/39 ,  G06F30/398 ,  G06F2119/06 ,  G06F2119/12

Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.

公开(公告)号：US11182527B2

公开(公告)日：2021-11-23

申请号：US16837449

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F30/392 ,  G06F30/39 ,  G06F30/30 ,  G06F30/347 ,  H01L27/02 ,  H01L29/06 ,  G06F111/20 ,  G06F30/398

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.

公开(公告)号：US10672709B2

公开(公告)日：2020-06-02

申请号：US15651165

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hiranmay Biswas ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/394 ,  H01L23/528 ,  H01L23/50 ,  H01L23/522 ,  G06F30/392 ,  G06F119/06

Abstract: A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of second power lines formed in the first metal layer and parallel to the first power lines, a plurality of third power lines formed in a second metal layer, and a plurality of fourth power lines formed in the second metal layer and parallel to the third power lines. The first and second power lines are interlaced in the first metal layer. The third and fourth power lines are interlaced in the second metal layer. Distances from the individual first power line to the two adjacent second power lines are the same, and distances from the individual third power line to the two adjacent fourth power lines are different.

公开(公告)号：US20200074030A1

公开(公告)日：2020-03-05

申请号：US16676210

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ravi Babu PITTU ,  Chung-Hsing Wang ,  Sung-Yen Yeh ,  Li Chung Hsu

IPC: G06F17/50

Abstract: A method and system for manufacturing a circuit is disclosed. In some embodiments, the system includes: at least one processor configured to: generate a first timing library for a first set of circuit elements for a first set of input parameters based on device characteristics for each of the circuit elements in the first set of circuit elements, and storing the determined device characteristics in a database; and generating a second timing library for a second set of circuit elements for a second set of input parameters based on device characteristics previously stored in the database for a first subset of the second set of circuit elements and determining device characteristics for a second subset of the second set of circuit elements using one of an aging simulation or a stress simulation; and a circuit generation system, coupled to the at least one processor, the circuit generation system configured to form a circuit on a substrate, wherein the circuit includes at least one of the first set of circuit elements or the second set of circuit elements.

公开(公告)号：US10565341B2

公开(公告)日：2020-02-18

申请号：US15878818

申请日：2018-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Hung Lin ,  Chung-Hsing Wang ,  Yuan-Te Hou

IPC: G06F17/50

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.