-
公开(公告)号：US11176303B2
公开(公告)日：2021-11-16
申请号：US16686711
申请日：2019-11-18
发明人： Yen-Hung Lin , Chung-Hsing Wang , Yuan-Te Hou
IPC分类号： G06F7/50 , G06F30/392 , G06F111/04
摘要： The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.
-
公开(公告)号：US11030381B2
公开(公告)日：2021-06-08
申请号：US16586658
申请日：2019-09-27
发明人： Cheng-Hua Liu , Yun-Xiang Lin , Yuan-Te Hou , Chung-Hsing Wang
IPC分类号： G06F30/398 , G06F30/367 , G06F30/20 , G06F30/39 , G06F119/10 , G06F30/392 , G06F119/18 , G06F111/20
摘要： A method is utilized to calculate a boundary leakage in a semiconductor device. A boundary is detected between a first cell and a second cell, which the first cell and the second cell are abutted to each other around the boundary. Attributes associated with cell edges of the first cell and the second cell are identified. A cell abutment case is identified based on the attributes associated with the cell edges of the first cell and the second cell. An expected boundary leakage between the first cell and the second cell is calculated based on leakage current values associated with the cell abutment case and leakage probabilities associated with the cell abutment case.
-
公开(公告)号：US10318698B2
公开(公告)日：2019-06-11
申请号：US15595863
申请日：2017-05-15
发明人： Yen-Hung Lin , Yuan-Te Hou , Chin-Chang Hsu
摘要： A method includes operations below. A layout of a circuit is converted to a first conflict graph. A first vertex and a second vertex in the first conflict graph are adjusted based on first data indicating a color patterns assignment for the circuit, in order to generate a second conflict graph, in which the first vertex indicates a first pattern in the layout, and the second vertex indicates a second pattern in the layout. According to the second conflict graph, a first color pattern is assigned to both of the first pattern and the second pattern, or the first color pattern is assigned to the first pattern and a second color pattern is assigned to the second pattern, in order to generate second data for fabricating the circuit.
-
公开(公告)号：US20180330034A1
公开(公告)日：2018-11-15
申请号：US15878818
申请日：2018-01-24
发明人： Yen-Hung Lin , Chung-Hsing Wang , Yuan-Te Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/06
摘要： The present disclosure describes an example method for cell placement in an integrated circuit layout design. The method includes retrieving, from a cell library, first and second cells each including a first local metal track proximate to a top boundary and a second local metal track proximate to a bottom boundary. The method includes placing, by a processor, the first and second cells in a layout area including global metal tracks of first and second types. Each global metal track of the first type and each global metal tracks of the second type alternate between one another in the layout area. The first and second local metal tracks of the first cell is aligned with adjacent first global metal track of the first and second types, respectively. The first and second local metal tracks of the second cell is aligned with adjacent second global metal track of the first and second types, respectively.
-
公开(公告)号：US09558312B2
公开(公告)日：2017-01-31
申请号：US14714394
申请日：2015-05-18
发明人： Lee-Chung Lu , Wen-Hao Chen , Yuan-Te Hou , Shen-Feng Chen , Meng-Fu You
IPC分类号： G06F17/50 , H01L23/528 , H01L27/10
CPC分类号： G06F17/5077 , G06F17/5036 , G06F17/5045 , G06F17/5072 , G06F17/5081 , G06F2217/82 , H01L23/5286 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.
摘要翻译： 标准单元半导体集成电路器件设计提供了标准单元半导体器件，其包括消耗更多功率的第一标准单元和用户定义的目标标准单元，或者包括与第一标准单元的操作特性不同的其他操作特性。 使用一个电源轨将标准电池单元路由到地线和电源线，并且使用第一电源轨和第二电源轨将目标电池路由到地线和电源线，以减轻任一电源轨道中的电迁移。 两个电源轨包括上电源轨和下电源轨。 中间导电层可以设置在上部和下部电源轨之间，以通过电池之间的横向互连提供信号路由。
-
公开(公告)号：US09035361B2
公开(公告)日：2015-05-19
申请号：US13871334
申请日：2013-04-26
发明人： Lee-Chung Lu , Wen-Hao Chen , Yuan-Te Hou , Shen-Feng Chen , Meng-Fu You
IPC分类号： H01L23/52 , H01L27/10 , G06F17/50 , H01L23/528
CPC分类号： G06F17/5077 , G06F17/5036 , G06F17/5045 , G06F17/5072 , G06F17/5081 , G06F2217/82 , H01L23/5286 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.
摘要翻译： 标准单元半导体集成电路器件设计提供了标准单元半导体器件，其包括消耗更多功率的第一标准单元和用户定义的目标标准单元，或者包括与第一标准单元的操作特性不同的其他操作特性。 使用一个电源轨将标准电池单元路由到地线和电源线，并且使用第一电源轨和第二电源轨将目标电池路由到地线和电源线，以减轻任一电力轨道中的电迁移。 两个电源轨包括上电源轨和下电源轨。 中间导电层可以设置在上部和下部电源轨之间，以通过电池之间的横向互连提供信号路由。
-
公开(公告)号：US11720738B2
公开(公告)日：2023-08-08
申请号：US17315023
申请日：2021-05-07
发明人： Cheng-Hua Liu , Yun-Xiang Lin , Yuan-Te Hou , Chung-Hsing Wang
IPC分类号： G06F30/30 , G06F30/398 , G06F30/367 , G06F30/20 , G06F30/39 , G06F119/10 , G06F30/392 , G06F119/18 , G06F111/20
CPC分类号： G06F30/398 , G06F30/20 , G06F30/367 , G06F30/39 , G06F30/392 , G06F2111/20 , G06F2119/10 , G06F2119/18
摘要： A system includes a library, a processor and an output interface. The library contains at least one leakage lookup table related to leakage current values for different cell abutment cases of abutted cells in a semiconductor device. The cell abutment cases are associated with terminal types of cell edges of the abutted cells. The processor is configured to perform an analysis to detect boundaries between the abutted cells, identify attributes associated with the terminal types of the cell edges, identify the cell abutment cases based on the attributes, and calculate maximal boundary leakages between the abutted cells based on leakage current values associated with the cell abutment cases and leakage probabilities associated with the cell abutment cases. The output interface is for outputting boundary leakages corresponding to the maximal boundary leakages in the semiconductor device. A method is also disclosed herein.
-
公开(公告)号：US11593546B2
公开(公告)日：2023-02-28
申请号：US17404511
申请日：2021-08-17
发明人： Kuang-Hung Chang , Yuan-Te Hou , Chung-Hsing Wang , Yung-Chin Hou
IPC分类号： G06F30/00 , G06F30/392 , G06F30/20 , G06F30/327 , H01L23/528 , H01L27/088 , G06F30/394
摘要： An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.
-
公开(公告)号：US20210326509A1
公开(公告)日：2021-10-21
申请号：US17363669
申请日：2021-06-30
发明人： Yen-Hung LIN , Yuan-Te Hou , Chung-Hsing Wang
IPC分类号： G06F30/392 , G06F30/39
摘要： A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
-
公开(公告)号：US20200226316A1
公开(公告)日：2020-07-16
申请号：US16837449
申请日：2020-04-01
发明人： Yen-Hung LIN , Chung-Hsing Wang , Yuan-Te Hou
IPC分类号： G06F30/392
摘要： The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes partitioning a layout area into one or more contiguous units, where each unit includes a plurality of placement sites. The method also includes mapping a first set of pin locations and a second set of pin locations to each of the one or more contiguous units. The method further includes placing a cell in the one or more contiguous units, where the cell is retrieved from a cell library that includes a plurality of pin locations for the cell. The placement of the cell is based on an allocation of one or more pins associated with the cell to at least one of a pin track from the first plurality of pin locations, a pin track from second plurality of pin locations, or a combination thereof.
-
-
-
-
-
-
-
-
-
搜索结果
35 条记录 (耗时 0.029 秒)
