公开(公告)号：US10790279B2

公开(公告)日：2020-09-29

申请号：US16656756

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L27/02 ,  H01L27/04 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.

公开(公告)号：US20200035672A1

公开(公告)日：2020-01-30

申请号：US16578299

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/06 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/522 ,  H01L23/48

Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.

公开(公告)号：US20190097013A1

公开(公告)日：2019-03-28

申请号：US15964572

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L29/4916 ,  H01L21/76 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0603 ,  H01L29/401

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US20190081041A1

公开(公告)日：2019-03-14

申请号：US16101843

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02 ,  H01L27/04 ,  H01L29/51

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/04 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first transistor gate stack is disposed in a low voltage region defined on a substrate. The first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate. A third transistor gate stack is disposed in a high voltage region defined on the substrate. The third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate. The third gate dielectric comprises an oxide component and a first interlayer dielectric layer.

公开(公告)号：US11569363B2

公开(公告)日：2023-01-31

申请号：US17192280

申请日：2021-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US20210193813A1

公开(公告)日：2021-06-24

申请号：US17192280

申请日：2021-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC: H01L29/49 ,  H01L21/76 ,  H01L21/768 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L21/8234

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US10964692B2

公开(公告)日：2021-03-30

申请号：US16578299

申请日：2019-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L21/00 ,  H01L27/06 ,  H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L21/48

Abstract: A three-dimensional (3D) integrated circuit (IC) and associated forming method are provided. In some embodiments, a second IC die is bonded to a first IC die through a second bonding structure and a first bonding structure at a bonding interface. The bonding encloses a seal-ring structure in a peripheral region of the 3D IC in the first and second IC dies. The seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. The bonding forms a plurality of through silicon via (TSV) coupling structures at the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure by electrically and correspondingly connects a first plurality of TSV wiring layers and inter-wire vias and a second plurality of TSV wiring layers and inter-wire vias.

公开(公告)号：US20200083343A1

公开(公告)日：2020-03-12

申请号：US16683530

申请日：2019-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC: H01L29/49 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/06 ,  H01L21/762 ,  H01L21/76

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US10510750B2

公开(公告)日：2019-12-17

申请号：US16101843

申请日：2018-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L27/02 ,  H01L27/04

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first transistor gate stack is disposed in a low voltage region defined on a substrate. The first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate. A third transistor gate stack is disposed in a high voltage region defined on the substrate. The third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate. The third gate dielectric comprises an oxide component and a first interlayer dielectric layer.

公开(公告)号：US20190296121A1

公开(公告)日：2019-09-26

申请号：US16437137

申请日：2019-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC: H01L29/49 ,  H01L29/06 ,  H01L21/76 ,  H01L21/762 ,  H01L29/40

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.