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公开(公告)号:US10516029B2
公开(公告)日:2019-12-24
申请号:US16437137
申请日:2019-06-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Fu-Jier Fan , Kong-Beng Thei , Yi-Sheng Chen , Szu-Hsien Liu
IPC: H01L29/49 , H01L29/06 , H01L29/40 , H01L27/088 , H01L21/8234 , H01L21/76 , H01L21/762
Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
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公开(公告)号:US20240047545A1
公开(公告)日:2024-02-08
申请号:US17879638
申请日:2022-08-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Ssu-Yu Liao , Ta-Wei Lin , Tsu-Hui Su , Chun-Hsiang Fan , Chun-Hsiang Fan , Kuo-Bin Huang
IPC: H01L29/423 , H01L29/06 , H01L29/786 , H01L21/306 , H01L29/66
CPC classification number: H01L29/42392 , H01L29/0673 , H01L29/78696 , H01L21/306 , H01L29/66477
Abstract: Fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. For example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. Consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.
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公开(公告)号:US20210193813A1
公开(公告)日:2021-06-24
申请号:US17192280
申请日:2021-03-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Fu-Jier Fan , Kong-Beng Thei , Yi-Sheng Chen , Szu-Hsien Liu
IPC: H01L29/49 , H01L21/76 , H01L21/768 , H01L21/762 , H01L27/088 , H01L29/06 , H01L29/40 , H01L21/8234
Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
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公开(公告)号:US20210043463A1
公开(公告)日:2021-02-11
申请号:US16532753
申请日:2019-08-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Ta-Wei Lin
IPC: H01L21/321 , H01L29/423 , H01L27/088 , H01L29/40
Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate. A first source/drain region and a second source/drain region are disposed in the semiconductor substrate and on opposite sides of the gate dielectric. A gate electrode is disposed over the gate dielectric. A first dishing prevention structure is embedded in the gate electrode, where a perimeter of the first dishing prevention structure is disposed within a perimeter of the gate electrode.
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公开(公告)号:US20200083343A1
公开(公告)日:2020-03-12
申请号:US16683530
申请日:2019-11-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Fu-Jier Fan , Kong-Beng Thei , Yi-Sheng Chen , Szu-Hsien Liu
IPC: H01L29/49 , H01L21/8234 , H01L27/088 , H01L29/40 , H01L29/06 , H01L21/762 , H01L21/76
Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
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公开(公告)号:US20190296121A1
公开(公告)日:2019-09-26
申请号:US16437137
申请日:2019-06-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Fu-Jier Fan , Kong-Beng Thei , Yi-Sheng Chen , Szu-Hsien Liu
IPC: H01L29/49 , H01L29/06 , H01L21/76 , H01L21/762 , H01L29/40
Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
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公开(公告)号:US10170334B2
公开(公告)日:2019-01-01
申请号:US15489875
申请日:2017-04-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Ta-Wei Lin
IPC: H01L21/321 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L29/40
Abstract: A semiconductor device includes a semiconductor substrate, a gate structure and at least one CMP resistant structure. The gate structure is over the semiconductor substrate. The CMP resistant structure is embedded in a top surface of the gate structure. The CMP resistant structure has a CMP resistance property different from a CMP resistance property of the gate structure.
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公开(公告)号:US11133226B2
公开(公告)日:2021-09-28
申请号:US16169220
申请日:2018-10-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Hsiao-Chin Tuan , Alexander Kalnitsky , Kong-Beng Thei , Chia-Hong Wu
IPC: H01L29/49 , H01L21/3213 , H01L29/423 , H01L21/28 , H01L29/66 , H01L21/8238 , H01L29/51 , H01L21/3105 , H01L29/08 , H01L27/092 , H01L29/45
Abstract: Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.
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公开(公告)号:US20190097013A1
公开(公告)日:2019-03-28
申请号:US15964572
申请日:2018-04-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Fu-Jier Fan , Kong-Beng Thei , Yi-Sheng Chen , Szu-Hsien Liu
IPC: H01L29/49 , H01L29/06 , H01L21/8234 , H01L27/088 , H01L29/40
CPC classification number: H01L29/4916 , H01L21/76 , H01L21/76229 , H01L21/823437 , H01L21/823481 , H01L27/088 , H01L29/0603 , H01L29/401
Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
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公开(公告)号:US20180301348A1
公开(公告)日:2018-10-18
申请号:US15489875
申请日:2017-04-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Ta-Wei Lin
IPC: H01L21/321 , H01L27/088 , H01L29/66 , H01L21/8234 , H01L29/40
CPC classification number: H01L21/3212 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/401 , H01L29/66545
Abstract: A semiconductor device includes a semiconductor substrate, a gate structure and at least one CMP resistant structure. The gate structure is over the semiconductor substrate. The CMP resistant structure is embedded in a top surface of the gate structure. The CMP resistant structure has a CMP resistance property different from a CMP resistance property of the gate structure.
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