公开(公告)号：US11302691B2

公开(公告)日：2022-04-12

申请号：US17009879

申请日：2020-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L27/02 ,  H01L27/04 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.

公开(公告)号：US11251286B2

公开(公告)日：2022-02-15

申请号：US16693670

申请日：2019-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

公开(公告)号：US10050033B1

公开(公告)日：2018-08-14

申请号：US15703116

申请日：2017-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L27/02 ,  H01L27/04 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first oxide component is disposed on a substrate within a medium voltage region. A first high-k dielectric component is disposed on the substrate within a low voltage region and a second high-k dielectric component disposed on the first oxide component within the medium voltage region. A first gate electrode separates from the substrate by the first high-k dielectric component. A second gate electrode separates from the substrate by the first oxide component and the second high-k dielectric component.

公开(公告)号：US09236326B2

公开(公告)日：2016-01-12

申请号：US14262582

申请日：2014-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Alexander Kalnitsky ,  Hsiao-Chin Tuan ,  Shih-Fen Huang ,  Hsin-Li Cheng ,  Felix Ying-Kit Tsui

IPC: H01L21/311 ,  H01L23/48 ,  H01L21/768 ,  H01L21/265 ,  H01L21/22

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括具有顶表面和底表面的晶片衬底，以及通过晶片衬底的顶表面和底表面由深沟槽绝缘体限定的晶片衬底中的导电柱。 制造半导体结构的方法包括以下步骤。 从晶片衬底的顶表面形成深沟槽以在晶片衬底中限定导电区域。 导电区域掺杂有掺杂剂。 深沟槽填充有绝缘材料以形成深沟槽绝缘体。 并且晶片衬底从晶片衬底的底表面变薄以暴露深沟槽绝缘体并隔离导电区域以形成导电柱。

公开(公告)号：US11527531B2

公开(公告)日：2022-12-13

申请号：US16412852

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Hsiao-Chin Tuan ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Shi-Chuang Hsiao ,  Yu-Hong Kuo

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

公开(公告)号：US11011619B2

公开(公告)日：2021-05-18

申请号：US16562953

申请日：2019-09-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

公开(公告)号：US11063038B2

公开(公告)日：2021-07-13

申请号：US16829176

申请日：2020-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L23/00 ,  H01L27/06 ,  H01L23/48 ,  H01L23/522 ,  H01L23/31 ,  H01L21/48

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure and closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.

公开(公告)号：US20200243516A1

公开(公告)日：2020-07-30

申请号：US16829176

申请日：2020-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Dun-Nian Yaung ,  Fu-Jier Fan ,  Hsing-Chih Lin ,  Hsiao-Chin Tuan ,  Jen-Cheng Liu ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/06 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/48

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure and closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.

公开(公告)号：US20200051975A1

公开(公告)日：2020-02-13

申请号：US16656756

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L27/02 ,  H01L27/04 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.

公开(公告)号：US10535752B2

公开(公告)日：2020-01-14

申请号：US15992817

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.