-
公开(公告)号：US11302691B2
公开(公告)日：2022-04-12
申请号：US17009879
申请日：2020-09-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kong-Beng Thei , Chien-Chih Chou , Fu-Jier Fan , Hsiao-Chin Tuan , Yi-Huan Chen , Alexander Kalnitsky , Yi-Sheng Chen
IPC: H01L27/088 , H01L21/8238 , H01L29/51 , H01L27/092 , H01L27/02 , H01L27/04 , H01L21/8234 , H01L29/66 , H01L29/423
Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage region and a high voltage region are integrated in a substrate. A low voltage transistor device is disposed in the low voltage region and comprises a low voltage gate electrode and a low voltage gate dielectric separating the low voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage gate electrode and the low voltage gate dielectric. A high voltage transistor device is disposed in the high voltage region and comprises a high voltage gate electrode disposed on the first interlayer dielectric layer.
-
公开(公告)号：US20210280577A1
公开(公告)日：2021-09-09
申请号：US17316155
申请日：2021-05-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Huan Chen , Kong-Beng Thei , Fu-Jier Fan , Ker-Hsiao Huo , Kau-Chu Lin , Li-Hsuan Yeh , Szu-Hsien Liu , Yi-Sheng Chen
IPC: H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/423 , H01L27/092
Abstract: A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.
-
公开(公告)号：US10950708B2
公开(公告)日：2021-03-16
申请号：US16683530
申请日：2019-11-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Fu-Jier Fan , Kong-Beng Thei , Yi-Sheng Chen , Szu-Hsien Liu
IPC: H01L29/49 , H01L29/06 , H01L29/40 , H01L27/088 , H01L21/8234 , H01L21/76 , H01L21/762 , H01L21/768
Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
-
公开(公告)号：US10340357B2
公开(公告)日：2019-07-02
申请号：US15964572
申请日：2018-04-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Fu-Jier Fan , Kong-Beng Thei , Yi-Sheng Chen , Szu-Hsien Liu
IPC: H01L29/49 , H01L29/06 , H01L29/40 , H01L27/088 , H01L21/8234
Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
-
公开(公告)号：US10164037B2
公开(公告)日：2018-12-25
申请号：US15475294
申请日：2017-03-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ker-Hsiao Huo , Kong-Beng Thei , Chih-Wen Albert Yao , Fu-Jier Fan , Chen-Liang Chu , Ta-Yuan Kung , Yi-Huan Chen , Yu-Bin Zhao , Ming-Ta Lei , Li-Hsuan Yeh
IPC: H01L29/423 , H01L21/28 , H01L29/40 , H01L29/06 , H01L29/08
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.
-
Patent Agency Ranking
公开(公告)号：US10050033B1
公开(公告)日：2018-08-14
申请号：US15703116
申请日：2017-09-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kong-Beng Thei , Chien-Chih Chou , Fu-Jier Fan , Hsiao-Chin Tuan , Yi-Huan Chen , Alexander Kalnitsky , Yi-Sheng Chen
IPC: H01L27/088 , H01L27/02 , H01L27/04 , H01L21/8238 , H01L27/092 , H01L29/51
Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first oxide component is disposed on a substrate within a medium voltage region. A first high-k dielectric component is disposed on the substrate within a low voltage region and a second high-k dielectric component disposed on the first oxide component within the medium voltage region. A first gate electrode separates from the substrate by the first high-k dielectric component. A second gate electrode separates from the substrate by the first oxide component and the second high-k dielectric component.
-
公开(公告)号：US11063038B2
公开(公告)日：2021-07-13
申请号：US16829176
申请日：2020-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kong-Beng Thei , Dun-Nian Yaung , Fu-Jier Fan , Hsing-Chih Lin , Hsiao-Chin Tuan , Jen-Cheng Liu , Alexander Kalnitsky , Yi-Sheng Chen
Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure and closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.
-
公开(公告)号：US20200243516A1
公开(公告)日：2020-07-30
申请号：US16829176
申请日：2020-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kong-Beng Thei , Dun-Nian Yaung , Fu-Jier Fan , Hsing-Chih Lin , Hsiao-Chin Tuan , Jen-Cheng Liu , Alexander Kalnitsky , Yi-Sheng Chen
Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a first IC die comprises a first bonding structure and a first interconnect structure over a first semiconductor substrate. A second IC die is disposed over the first IC die and comprises a second bonding structure and a second interconnect structure over a second semiconductor substrate. A seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate. A plurality of through silicon via (TSV) coupling structures is arranged in the peripheral region of the 3D IC along an inner perimeter of the seal-ring structure and closer to the 3D IC than the seal-ring structure. The plurality of TSV coupling structures respectively comprises a TSV disposed in the second semiconductor substrate and electrically coupling to the 3D IC through a stack of TSV wiring layers and inter-wire vias.
-
公开(公告)号：US20200051975A1
公开(公告)日：2020-02-13
申请号：US16656756
申请日：2019-10-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kong-Beng Thei , Chien-Chih Chou , Fu-Jier Fan , Hsiao-Chin Tuan , Yi-Huan Chen , Alexander Kalnitsky , Yi-Sheng Chen
IPC: H01L27/088 , H01L21/8238 , H01L29/51 , H01L27/092 , H01L27/02 , H01L27/04 , H01L21/8234 , H01L29/66 , H01L29/423
Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.
-
公开(公告)号：US10516029B2
公开(公告)日：2019-12-24
申请号：US16437137
申请日：2019-06-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Huan Chen , Chien-Chih Chou , Ta-Wei Lin , Fu-Jier Fan , Kong-Beng Thei , Yi-Sheng Chen , Szu-Hsien Liu
IPC: H01L29/49 , H01L29/06 , H01L29/40 , H01L27/088 , H01L21/8234 , H01L21/76 , H01L21/762
Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.018 seconds)
