公开(公告)号：US20240274465A1

公开(公告)日：2024-08-15

申请号：US18643212

申请日：2024-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Kai Hsiao ,  Han-De Chen ,  Tsai-Yu Huang ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/28008 ,  H01L21/76227 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/0649

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

公开(公告)号：US20240120314A1

公开(公告)日：2024-04-11

申请号：US18390439

申请日：2023-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/265 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/7806 ,  H01L25/50

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.

公开(公告)号：US11855040B2

公开(公告)日：2023-12-26

申请号：US17497050

申请日：2021-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L21/265 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/83 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/7806 ,  H01L25/50

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.

公开(公告)号：US20230019415A1

公开(公告)日：2023-01-19

申请号：US17648236

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Cheng-I Chu ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/66

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

公开(公告)号：US20220367410A1

公开(公告)日：2022-11-17

申请号：US17497050

申请日：2021-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/265 ,  H01L21/78 ,  H01L21/683 ,  H01L25/00

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.

公开(公告)号：US20220230926A1

公开(公告)日：2022-07-21

申请号：US17150018

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Yu Huang ,  Han-De Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/764

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

公开(公告)号：US20250149378A1

公开(公告)日：2025-05-08

申请号：US19014922

申请日：2025-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Chen-Fong Tsai ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/67 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D86/00

Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

公开(公告)号：US12255171B2

公开(公告)日：2025-03-18

申请号：US17412768

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/683

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10−2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

公开(公告)号：US20250089313A1

公开(公告)日：2025-03-13

申请号：US18463466

申请日：2023-09-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Fong Tsai ,  Han-De Chen ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method includes: epitaxially growing a first multi-layer stack over a first substrate; epitaxially growing a second multi-layer stack over a second substrate; and bonding the first multi-layer stack to the second multi-layer stack. The first substrate and the second substrate have different crystalline orientations. The method further includes patterning the first multi-layer stack and the second multi-layer stack to form a fin, the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures alternatingly stacked with second dummy nanostructure; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures.

公开(公告)号：US12230532B2

公开(公告)日：2025-02-18

申请号：US17459509

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Chen-Fong Tsai ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/67 ,  H01L27/12 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.