公开(公告)号：US11271150B2

公开(公告)日：2022-03-08

申请号：US16866114

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Chien-Chung Huang ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Hui-Hsien Wei

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.

公开(公告)号：US10651373B2

公开(公告)日：2020-05-12

申请号：US16194124

申请日：2018-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Chien-Chung Huang ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Hui-Hsien Wei

IPC: H01L27/24 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.

公开(公告)号：US11800812B2

公开(公告)日：2023-10-24

申请号：US17688370

申请日：2022-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Chien-Chung Huang ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Hui-Hsien Wei

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/10 ,  H10B61/22 ,  H10B61/00 ,  H10N50/80

Abstract: An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.

公开(公告)号：US11665971B2

公开(公告)日：2023-05-30

申请号：US17408648

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Yu-Shu Chen ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Chih-Yuan Ting

IPC: H01L21/00 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02

Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

公开(公告)号：US20210098695A1

公开(公告)日：2021-04-01

申请号：US17120613

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Qiang Fu

IPC: H01L43/12 ,  H01L43/02

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.