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公开(公告)号：US12219879B2
公开(公告)日：2025-02-04
申请号：US18521399
申请日：2023-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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公开(公告)号：US20210384418A1
公开(公告)日：2021-12-09
申请号：US17408648
申请日：2021-08-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Sin-Yi Yang , Chen-Jung Wang , Yu-Shu Chen , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Chih-Yuan Ting
Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
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公开(公告)号：US20250133967A1
公开(公告)日：2025-04-24
申请号：US19001145
申请日：2024-12-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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公开(公告)号：US11856865B2
公开(公告)日：2023-12-26
申请号：US17869335
申请日：2022-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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公开(公告)号：US11545619B2
公开(公告)日：2023-01-03
申请号：US16934341
申请日：2020-07-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsing-Hsiang Wang , Han-Ting Lin , Yu-Feng Yin , Sin-Yi Yang , Chen-Jung Wang , Yin-Hao Wu , Kun-Yi Li , Meng-Chieh Wen , Lin-Ting Lin , Jiann-Horng Lin , An-Shen Chang , Huan-Just Lin
Abstract: A method for forming a memory device structure is provided. The method includes providing a substrate, a first dielectric layer, a conductive via, a magnetic tunnel junction cell, a first etch stop layer, and a first spacer layer. The substrate has a first region and a second region, the first dielectric layer is over the substrate, the conductive via passes through the first dielectric layer over the first region. The method includes removing the first etch stop layer, which is not covered by the first spacer layer. The method includes removing the first dielectric layer, which is not covered by the first etch stop layer.
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Patent Agency Ranking
公开(公告)号：US20230263068A1
公开(公告)日：2023-08-17
申请号：US18303240
申请日：2023-04-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Sin-Yi Yang , Chen-Jung Wang , Yu-Shu Chen , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Chih-Yuan Ting
Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
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公开(公告)号：US10770345B2
公开(公告)日：2020-09-08
申请号：US16112955
申请日：2018-08-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tai-Yen Peng , Chang-Sheng Lin , Chien-Chung Huang , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Han-Ting Lin , Chih-Yuan Ting , Jyu-Horng Shieh
IPC: H01L43/12 , G11C11/16 , H01L27/22 , H01L43/02 , H01L43/08 , H01L21/768 , H01L21/3105 , H01L27/24
Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
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公开(公告)号：US20240099150A1
公开(公告)日：2024-03-21
申请号：US18521399
申请日：2023-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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公开(公告)号：US20220367794A1
公开(公告)日：2022-11-17
申请号：US17869335
申请日：2022-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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公开(公告)号：US11411176B2
公开(公告)日：2022-08-09
申请号：US17120613
申请日：2020-12-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tai-Yen Peng , Yu-Shu Chen , Sin-Yi Yang , Chen-Jung Wang , Chien Chung Huang , Han-Ting Lin , Jyu-Horng Shieh , Qiang Fu
Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.
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