公开(公告)号：US20240251568A1

公开(公告)日：2024-07-25

申请号：US18626670

申请日：2024-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  G11C11/1659

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

公开(公告)号：US20230263068A1

公开(公告)日：2023-08-17

申请号：US18303240

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Yu-Shu Chen ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Chih-Yuan Ting

IPC: H10N50/01 ,  H10B61/00

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

公开(公告)号：US10770345B2

公开(公告)日：2020-09-08

申请号：US16112955

申请日：2018-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen Peng ,  Chang-Sheng Lin ,  Chien-Chung Huang ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Han-Ting Lin ,  Chih-Yuan Ting ,  Jyu-Horng Shieh

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L21/768 ,  H01L21/3105 ,  H01L27/24

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.

公开(公告)号：US20250133967A1

公开(公告)日：2025-04-24

申请号：US19001145

申请日：2024-12-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Qiang Fu

IPC: H10N50/01 ,  H10N50/80

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

公开(公告)号：US11980040B2

公开(公告)日：2024-05-07

申请号：US17346855

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  G11C11/16

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  G11C11/1659

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

公开(公告)号：US11856865B2

公开(公告)日：2023-12-26

申请号：US17869335

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Yu-Shu Chen ,  Sin-Yi Yang ,  Chen-Jung Wang ,  Chien Chung Huang ,  Han-Ting Lin ,  Jyu-Horng Shieh ,  Qiang Fu

IPC: H10N50/01 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10N50/80

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

公开(公告)号：US20210313396A1

公开(公告)日：2021-10-07

申请号：US17346855

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yen Peng ,  Tsung-Hsien Chang ,  Yu-Shu Chen ,  Chih-Yuan Ting ,  Jyu-Horng Shieh ,  Chung-Te Lin

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08

Abstract: A semiconductor device includes a substrate; a memory array over the substrate, the memory array including first magnetic tunnel junctions (MTJs), where the first MTJs are in a first dielectric layer over the substrate; and a resistor circuit over the substrate, the resistor circuit including second MTJs, where the second MTJs are in the first dielectric layer.

公开(公告)号：US20200303204A1

公开(公告)日：2020-09-24

申请号：US16895525

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hao Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.

公开(公告)号：US10002790B2

公开(公告)日：2018-06-19

申请号：US15243663

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yungtzu Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L21/76879 ,  H01L21/02126 ,  H01L21/02186 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L2221/1063

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a semiconductor substrate and forming a hard mask layer over the material layer. The hard mask layer contains metal. The method also includes forming an opening in the hard mask layer using a plasma etching process, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The method further includes etching the material layer through the opening in the hard mask layer to form a feature opening in the material layer.

公开(公告)号：US09735028B2

公开(公告)日：2017-08-15

申请号：US14789337

申请日：2015-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Hung-Hao Chen ,  Yu-Shu Chen ,  Yu-Cheng Liu

IPC: H01L21/311 ,  H01L23/48 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/31144 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/53295

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and forming a bottom layer, a middle layer, and a top layer on the substrate. The method also includes patterning the top layer to form a patterned top layer and patterning the middle layer by a patterning process including a plasma process to form a patterned middle layer. The plasma process is performed by using a mixed gas including hydrogen gas (H2). The method further includes controlling a flow rate of the hydrogen gas (H2) to improve an etching selectivity of the middle layer to the top layer, and the patterned middle layer includes a first portion and a second portion parallel to the first portion, and a pitch is between the first portion and the second portion.