公开(公告)号：US11515474B2

公开(公告)日：2022-11-29

申请号：US17112861

申请日：2020-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

公开(公告)号：US20210391534A1

公开(公告)日：2021-12-16

申请号：US17461132

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Wu Meng Yu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Han-Ting Tsai ,  Yu-Jen Chien

IPC: H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.

公开(公告)号：US10535816B2

公开(公告)日：2020-01-14

申请号：US16059777

申请日：2018-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Szu-Ping Tung ,  Szu-Hua Wu ,  Shing-Chyang Pan ,  Meng-Yu Wu

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A via structure, a MRAM device using the via structure and a method for fabricating the MRAM device are provided. In the method for fabricating the MRAM device, at first, a first dielectric layer is deposited over a transistor. Then, a contact is formed in the first dielectric layer and electrically connected to the transistor. Thereafter, a metal nitride layer is deposited over the first dielectric layer and the contact. Then, an etch stop layer is deposited over the metal nitride layer. Thereafter, a second dielectric layer is deposited over the etch stop layer. Then, a via structure is formed in the second dielectric layer, the etch stop layer, and the metal nitride layer and landing on the contact. Thereafter, a memory stack is formed over the via structure.

公开(公告)号：US11985904B2

公开(公告)日：2024-05-14

申请号：US17168974

申请日：2021-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Jen Chien ,  Jung-Tang Wu ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Meng-Yu Wu

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

公开(公告)号：US20240065110A1

公开(公告)日：2024-02-22

申请号：US18501843

申请日：2023-11-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Meng Yu Wu ,  Szu-Hua Wu ,  Chin-Szu Lee

IPC: H10N50/01 ,  H10B61/00

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/10

Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.

公开(公告)号：US11844283B2

公开(公告)日：2023-12-12

申请号：US17240346

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Meng Yu Wu ,  Szu-Hua Wu ,  Chin-Szu Lee

IPC: H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.

公开(公告)号：US20230369044A1

公开(公告)日：2023-11-16

申请号：US18360259

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Yu-Jen Chien ,  Szu-Hua Wu ,  Chin-Szu Lee ,  Yao-Shien Huang

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/04 ,  H10B61/00 ,  H10N50/01

CPC classification number: H01L21/0234 ,  H01L21/28088 ,  H01L21/044 ,  H10B61/00 ,  H10N50/01

Abstract: A method of forming a semiconductor structure includes forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer and performing a smoothing treatment on the first TE layer. The smoothing treatment is performed in situ after the forming first TE layer. The smoothing treatment removes spike point defects from the first TE layer. Additional TE layers may be formed over the first TE layer.

公开(公告)号：US20210249591A1

公开(公告)日：2021-08-12

申请号：US17240346

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Tang Wu ,  Meng Yu Wu ,  Szu-Hua Wu ,  Chin-Szu Lee

IPC: H01L43/12 ,  H01L27/22

Abstract: Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.

公开(公告)号：US10727118B2

公开(公告)日：2020-07-28

申请号：US15964430

申请日：2018-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Pao-Sheng Chen ,  Pei-Hsuan Lee ,  Szu-Hua Wu ,  Chih-Chien Chi

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/02

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.