公开(公告)号：US09356136B2

公开(公告)日：2016-05-31

申请号：US13788524

申请日：2013-03-07

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Wei-Yuan Lu ,  Lilly Su ,  Chun-Hung Huang ,  Chii-Horng Li ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7816 ,  H01L21/823418 ,  H01L29/0843 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66053 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848

Abstract: Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.

Abstract translation: 具有场效应晶体管的集成电路器件具有包括第一和第二层的源区和漏区。 第一层形成在通道区域的平面之下。 第一层包括具有小于硅的晶格结构的掺杂硅和碳。 第二层形成在第一层上并且在沟道区的平面上方上升。 第二层由包括掺杂的外延生长的硅的材料形成。 第二层的碳原子分数小于第一层的一半。 第一层形成在通道区域的表面下方至少10nm的深度。 该结构有助于形成非常浅的结的源极和漏极扩展区域。 这些装置提供具有低电阻的源和漏极，同时抵抗短沟道效应。

公开(公告)号：US20240387665A1

公开(公告)日：2024-11-21

申请号：US18789227

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L29/417 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

公开(公告)号：US12107133B2

公开(公告)日：2024-10-01

申请号：US17379265

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L29/417 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/7851

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.

公开(公告)号：US20210202309A1

公开(公告)日：2021-07-01

申请号：US17201637

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522

Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

公开(公告)号：US10693004B2

公开(公告)日：2020-06-23

申请号：US16163970

申请日：2018-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Fu-Hsiang Su ,  Ke-Jing Yu ,  Chih-Hong Hwang ,  Jyh-Huei Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack over a substrate and an insulating capping layer over the gate stack. The semiconductor device structure also includes a source/drain contact structure adjacent to the gate stack and having an upper surface that is substantially level with the upper surface of the insulating capping layer. The semiconductor device structure also includes a first via structure passing through the insulating capping layer and electrically connected to the gate stack, and a second via structure above and electrically connected to the source/drain contact structure. The first via structure and the second via structure have different vertical heights.

公开(公告)号：US10262878B2

公开(公告)日：2019-04-16

申请号：US16155186

申请日：2018-10-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Jung Liu ,  Chih-Pin Tsao ,  Chia-Wei Soong ,  Jyh-Huei Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC: H01L27/088 ,  H01L21/67 ,  H01L29/78 ,  H01L23/485 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/027 ,  H01J37/32

Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.

公开(公告)号：US10109507B2

公开(公告)日：2018-10-23

申请号：US15609199

申请日：2017-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Jung Liu ,  Chih-Pin Tsao ,  Chia-Wei Soong ,  Jyh-Huei Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC: H01L21/84 ,  H01L21/67 ,  H01L21/311 ,  H01L21/027 ,  H01J37/32 ,  H01L21/3065

Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.

公开(公告)号：US12154856B2

公开(公告)日：2024-11-26

申请号：US17873782

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Yi-Ju Chen ,  Jyh-Huei Chen

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

公开(公告)号：US11508616B2

公开(公告)日：2022-11-22

申请号：US17201637

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

公开(公告)号：US20210351273A1

公开(公告)日：2021-11-11

申请号：US17379265

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Tsai ,  Jyh-Huei Chen

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238

Abstract: FinFET devices with source/drain contacts with reduced resistance/capacitance power loss and with an enhanced processing window between the source/drain contacts and a gate via and methods of manufacture are described herein. A metal riser may be formed in a first recess of a source/drain contact of a first material. The metal riser and a contact via may be formed from a second material and the contact via may be formed over the metal riser to provide a hybrid source/drain contact of a finFET with a wide surface contact area at an interface between the source/drain contact and the metal riser. A dielectric fill material and/or a conformal contact etch stop layer may be used to form an isolation region in a second recess of the source/drain contact to extend a processing window disposed between the isolation region and a gate contact of the finFET.