公开(公告)号：US20190109206A1

公开(公告)日：2019-04-11

申请号：US16208157

申请日：2018-12-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung CHEN ,  Kang-Min KUO ,  Wen-Hsin CHAN

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first fin structure and a second fin structure over a semiconductor substrate, and forming a mask layer covering the first fin structure and the second fin structure. The method also includes performing a first etching operation using the second fin structure as an etch stop layer to partially remove the mask layer such that the etch stop layer protrudes from the mask layer after the first etching operation. The method further includes partially removing the second fin structure using a second etching operation after the first etching operation.

公开(公告)号：US20180197969A1

公开(公告)日：2018-07-12

申请号：US15911884

申请日：2018-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei YEH ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/45 ,  H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L29/518 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.

公开(公告)号：US20180158727A1

公开(公告)日：2018-06-07

申请号：US15888999

申请日：2018-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia HSIEH ,  Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/311 ,  H01L29/161 ,  H01L29/45 ,  H01L23/485 ,  H01L29/16 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L23/532

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US20200075401A1

公开(公告)日：2020-03-05

申请号：US16678666

申请日：2019-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Jia HSIEH ,  Long-Jie HONG ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/485 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02 ,  H01L29/45 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

公开(公告)号：US20180090561A1

公开(公告)日：2018-03-29

申请号：US15830979

申请日：2017-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20170154954A1

公开(公告)日：2017-06-01

申请号：US14954524

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei LIN ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20170141205A1

公开(公告)日：2017-05-18

申请号：US14940832

申请日：2015-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ruei YEH ,  Chih-Lin WANG ,  Kang-Min KUO

IPC: H01L29/51 ,  H01L29/45 ,  H01L21/02 ,  H01L29/40 ,  H01L21/768 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/518 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a metal gate electrode structure over the semiconductor substrate. The semiconductor device structure includes an insulating layer over the semiconductor substrate and surrounding the metal gate electrode structure. The semiconductor device structure includes a first metal nitride layer over a first top surface of the metal gate electrode structure and in direct contact with the metal gate electrode structure. The first metal nitride layer includes a nitride material of the metal gate electrode structure.

公开(公告)号：US20170033194A1

公开(公告)日：2017-02-02

申请号：US14815349

申请日：2015-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lung CHEN ,  Kang-Min KUO ,  Wen-Hsin CHAN

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/76232 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的第一鳍结构。 半导体器件结构还包括半导体衬底上的第二鳍结构。 第二鳍结构具有比第一鳍结构低的高度。 第二鳍结构包括第一侧壁和第二侧壁，并且第一侧壁和第二侧壁围绕第二鳍结构的凹陷。

公开(公告)号：US20160293702A1

公开(公告)日：2016-10-06

申请号：US14704324

申请日：2015-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Lung CHEN ,  Kang-Min KUO ,  Wen-Hsin CHAN

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate. The semiconductor device structure also includes a source/drain structure over the semiconductor substrate, and the source/drain structure includes a dopant. The semiconductor device structure further includes a channel region under the gate stack. In addition, the semiconductor device structure includes a semiconductor layer surrounding the source/drain structure. The semiconductor layer is configured to prevent the dopant from entering the channel region.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括半导体衬底上的栅极堆叠。 半导体器件结构还包括半导体衬底上的源极/漏极结构，并且源极/漏极结构包括掺杂剂。 该半导体器件结构还包括在栅极堆叠下面的沟道区域。 此外，半导体器件结构包括围绕源极/漏极结构的半导体层。 半导体层被配置为防止掺杂剂进入沟道区域。

公开(公告)号：US20160190240A1

公开(公告)日：2016-06-30

申请号：US14718841

申请日：2015-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cong-Min FANG ,  Kang-Min KUO ,  Shi-Min WU

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229 ,  H01L29/0657

Abstract: A semiconductor structure includes a semiconductor substrate, a first active area, a second active area, a first trench, at least one raised portion, and a first dielectric. The first active area is in the semiconductor substrate. The second active area is in the semiconductor substrate. The first trench is in the semiconductor substrate and separates the first active area and the second active area from each other. The raised portion is raised from the semiconductor substrate and is disposed in the first trench. The first dielectric is in the first trench and covers the raised portion.

Abstract translation: 半导体结构包括半导体衬底，第一有源区，第二有源区，第一沟槽，至少一个凸起部分和第一电介质。 第一有源区在半导体衬底中。 第二有源区在半导体衬底中。 第一沟槽位于半导体衬底中并将第一有源区和第二有源区彼此分离。 凸起部分从半导体衬底升高并设置在第一沟槽中。 第一电介质在第一沟槽中并覆盖凸起部分。