-
1.
公开(公告)号:US20200343360A1
公开(公告)日:2020-10-29
申请号:US16928942
申请日:2020-07-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lung CHEN , Kang-Min KUO , Wen-Hsin CHAN
IPC: H01L29/66 , H01L29/78 , H01L29/06 , H01L21/762 , H01L21/8234
Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation.
-
公开(公告)号:US20200295136A1
公开(公告)日:2020-09-17
申请号:US16889511
申请日:2020-06-01
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Lung CHEN , Kang-Min KUO , Long-Jie HONG
IPC: H01L29/08 , H01L29/66 , H01L21/3065 , H01L21/02 , H01L29/167 , H01L29/165 , H01L29/78
Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.
-
3.
公开(公告)号:US20170053868A1
公开(公告)日:2017-02-23
申请号:US14832655
申请日:2015-08-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Shu-Cheng LIN , Chih-Lin WANG , Kang-Min KUO
IPC: H01L23/522 , H01L21/02 , H01L23/532 , H01L21/311 , H01L23/528 , H01L21/768
CPC classification number: H01L21/76877 , H01L21/31116 , H01L21/76802 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure.
Abstract translation: 提供半导体器件结构。 半导体器件结构包括衬底。 半导体器件结构包括在衬底上的第一导电结构。 半导体器件结构包括在衬底上的第一介电层。 第一电介质层具有暴露第一导电结构的第一开口。 半导体器件结构包括覆盖第一开口的内壁并与第一介电层直接接触的密封层。 密封层包括包含氧化合物的电介质材料。 半导体器件结构包括填充在第一开口中并被密封层包围的第二导电结构。 第二导电结构电连接到第一导电结构。
-
公开(公告)号:US20200058756A1
公开(公告)日:2020-02-20
申请号:US16665296
申请日:2019-10-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chi-Ruei YEH , Chih-Lin WANG , Kang-Min KUO
IPC: H01L29/51 , H01L29/78 , H01L29/45 , H01L29/423 , H01L29/40 , H01L21/768 , H01L21/02 , H01L29/49 , H01L29/66
Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.
-
公开(公告)号:US20180342514A1
公开(公告)日:2018-11-29
申请号:US16055526
申请日:2018-08-06
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Chih-Wei LIN , Chih-Lin WANG , Kang-Min KUO , Cheng-Wei LIAN
IPC: H01L27/092 , H01L29/49 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/51 , H01L21/28 , H01L21/8238
CPC classification number: H01L27/092 , H01L21/28088 , H01L21/28176 , H01L21/823842 , H01L29/401 , H01L29/42364 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6656
Abstract: Methods for forming a semiconductor structure are provided. The method includes forming a first dummy gate structure and forming first spacers over a sidewall of the first dummy gate structure. The method includes removing the first dummy gate structure to form a first trench between the first spacers and forming a first capping layer in the first trench. A first portion of the first capping layer covers a sidewall of the first trench and a second portion of the first capping layer covers a bottom surface of the first trench. The method further includes oxidizing a sidewall of the first portion of the first capping layer and a top surface of the second portion of the first capping layer to form a first capping oxide layer and forming a first work function metal layer and forming a first gate electrode layer over the first work function metal layer.
-
公开(公告)号:US20170373143A1
公开(公告)日:2017-12-28
申请号:US15700115
申请日:2017-09-09
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Cong-Min FANG , Kang-Min KUO , Shi-Min WU
IPC: H01L29/06 , H01L21/762
CPC classification number: H01L29/0649 , H01L21/76229 , H01L29/0657
Abstract: A method of manufacturing a semiconductor structure includes the following steps. A first raised portion is formed on a semiconductor substrate. The height of the first raised portion is reduced, and a dielectric material is formed over the first raised portion. The dielectric material is annealed such that the first raised portion is tilted.
-
公开(公告)号:US20170221758A1
公开(公告)日:2017-08-03
申请号:US15489947
申请日:2017-04-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Shu-Cheng LIN , Chih-Lin WANG , Kang-Min KUO
IPC: H01L21/768 , H01L23/532 , H01L21/311 , H01L23/522 , H01L21/02
CPC classification number: H01L21/76877 , H01L21/31116 , H01L21/76802 , H01L21/76814 , H01L21/76831 , H01L23/5226 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L23/53295
Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a substrate. The first dielectric layer surrounds the first conductive structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the first conductive structure. The method includes forming a seal layer over the first conductive structure and an inner wall of the opening. The seal layer is in direct contact with the first dielectric layer and the second dielectric layer, and the seal layer includes a dielectric material comprising an oxygen compound. The method includes removing the seal layer over the first conductive structure. The method includes filling a second conductive structure into the opening.
-
8.
公开(公告)号:US20200066873A1
公开(公告)日:2020-02-27
申请号:US16668787
申请日:2019-10-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Lung CHEN , Kang-Min KUO , Wen-Hsin CHAN
IPC: H01L29/66 , H01L29/78 , H01L29/06 , H01L21/762 , H01L21/8234
Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure over a semiconductor substrate, and forming a mask layer covering the dummy fin structure. The method further includes irradiating the mask layer, so that the mask layer is divided into an unirradiated portion and an irradiated portion, and the irradiated portion is over the dummy fin structure. The method also includes removing a top portion of the irradiated portion and a top portion of the dummy fin structure by a first etching operation, such that the dummy fin structure has a convex top surface after the first etching operation. The method includes removing a middle portion of the dummy fin structure by a second etching operation, such that the dummy fin structure has a concave top surface after the second etching operation.
-
公开(公告)号:US20200020771A1
公开(公告)日:2020-01-16
申请号:US16036302
申请日:2018-07-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Lung CHEN , Kang-Min KUO , Long-Jie HONG
IPC: H01L29/08 , H01L29/66 , H01L21/3065 , H01L21/02 , H01L29/167 , H01L29/165 , H01L29/78
Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure has a channel region and a source/drain region. A gate structure is formed over the channel region of the fin structure. A first source/drain etching is performed to recess the source/drain region of the fin structure. After the first source/drain etching, a second source/drain etching is performed to further recess the source/drain region of the fin structure. After the second source/drain etching, a third source/drain etching is performed to further recess the source/drain region of the fin structure, thereby forming a source/drain recess. One or more epitaxial layers are formed in the source/drain recess. The first source/drain etching is isotropic etching and the second source/drain etching is anisotropic etching.
-
公开(公告)号:US20190355814A1
公开(公告)日:2019-11-21
申请号:US16525346
申请日:2019-07-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Cong-Min FANG , Kang-Min KUO , Shi-Min WU
IPC: H01L29/06 , H01L21/762
Abstract: A semiconductor device includes a semiconductive substrate, a first semiconductive fin and a second semiconductive fin extending upwards from the semiconductive substrate, an isolation structure at least partially between the first semiconductive fin and the second semiconductive fin, a first semiconductive raised portion and a second semiconductive raised portion. The first semiconductive raised portion extends upwards from the semiconductive substrate, is buried under the isolation structure, and is between the first semiconductive fin and the second semiconductive fin. A top surface of the first semiconductive fin is higher than a top surface of the first semiconductive raised portion. The second semiconductive raised portion extends upwards from the semiconductive substrate, is buried under the isolation structure, and is between the first semiconductive raised portion and the second semiconductive fin.
-
-
-
-
-
-
-
-
-