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    Semiconductor package and manufacturing method thereof
    11.
    发明授权
    Semiconductor package and manufacturing method thereof 有权

    公开(公告)号：US11508640B2

    公开(公告)日：2022-11-22

    申请号：US16874621

    申请日：2020-05-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Wen-Lin Chen

    IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

    INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
    13.
    发明申请
    INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200328173A1

    公开(公告)日：2020-10-15

    申请号：US16914478

    申请日：2020-06-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

    IPC: H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L21/683

    Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

    Integrated fan-out package and manufacturing method thereof
    16.
    发明授权
    Integrated fan-out package and manufacturing method thereof 有权

    公开(公告)号：US10157871B1

    公开(公告)日：2018-12-18

    申请号：US15730760

    申请日：2017-10-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/522 ,  H01L23/532

    Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a plurality of conductive pillars, a seed layer, and a plurality of conductive bumps. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die and includes a plurality of dielectric layers that are sequentially stacked and a plurality of conductive patterns sandwiched between the dielectric layers. A Young's modulus of the dielectric layer farthest away from the die is higher than a Young's modulus of each of the rest of the dielectric layers. The conductive patterns are electrically connected to each other. The conductive pillars are disposed on and electrically connected to the redistribution structure. The seed layer is located between the conductive pillars and the redistribution structure. The conductive bumps are disposed on the plurality of conductive pillars.

    Integrated fan-out package and manufacturing method thereof
    17.
    发明授权
    Integrated fan-out package and manufacturing method thereof 有权

    公开(公告)号：US11355461B2

    公开(公告)日：2022-06-07

    申请号：US16914478

    申请日：2020-06-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

    IPC: H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L21/683

    Abstract: An integrated fan-out package includes a die, an encapsulant, a seed layer, a conductive pillar, a redistribution structure, and a buffer layer. The encapsulant encapsulates the die. The seed layer and the conductive pillar are sequentially stacked over the die and the encapsulant. The redistribution structure is over the die and the encapsulant. The redistribution structure includes a conductive pattern and a dielectric layer. The conductive pattern is directly in contact with the seed layer and the dielectric layer covers the conductive pattern and surrounds the seed layer and the conductive pillar. The buffer layer is disposed over the redistribution structure. The seed layer is separate from the dielectric layer by the buffer layer, and a Young's modulus of the buffer layer is higher than a Young's modulus of the dielectric layer of the redistribution structure.

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