公开(公告)号：US20200313659A1

公开(公告)日：2020-10-01

申请号：US16900854

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Pen GUO ,  Chi-Lin LIU ,  Shang-Chih HSIEH ,  Jerry Chang-Jui KAO ,  Li-Chun TIEN ,  Lee-Chung LU

IPC: H03K3/0233 ,  H03K23/58 ,  H03K19/094 ,  H03K3/01 ,  H01L27/02 ,  H03K3/356 ,  H03K3/3562 ,  H01L27/118 ,  H01L27/092

Abstract: A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

公开(公告)号：US20150249080A1

公开(公告)日：2015-09-03

申请号：US14714369

申请日：2015-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Yu MA ,  Bo-Ting CHEN ,  Ting Yu CHEN ,  Kuo-Ji CHEN ,  Li-Chun TIEN

IPC: H01L27/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L27/06 ,  H01L27/118

CPC classification number: H01L27/0288 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0629 ,  H01L27/11807 ,  H01L28/20 ,  H01L28/24

Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

Abstract translation: 集成电路包括半导体器件层，其包括在栅电极线之间具有固定栅电极间距的标准单元配置和在标准单元配置的固定栅电极间距之间由金属形成的电阻。 在一个实施例中，集成电路可以是具有由金属形成的电阻器的交叉域标准单元的充电器件模型（CDM）静电放电（ESD）保护电路。 制造集成电路的方法包括：形成由栅电极间距分开的多个栅极电极线，以形成芯标准电池器件，在栅电极间距内施加至少第一金属层以形成电阻器的一部分，以及 施加至少第二金属层以耦合到第一金属层以形成电阻器的另一部分。

公开(公告)号：US20140264894A1

公开(公告)日：2014-09-18

申请号：US13888405

申请日：2013-05-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Chun TIEN ,  Chen-Chi WU ,  Kuo-Ji CHEN

IPC: G06F17/50 ,  H01L21/033

CPC classification number: G06F17/50 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L21/0337 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

Abstract: An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed.

Abstract translation: 一种集成电路包括被配置为具有第一电压电位的器件的第一导电结构，该器件的第二导电结构被配置为具有不同于第一电压电位的第二电压电位，以及设置在并分离之间的维持和平结构 第一导电结构和第二导电结构。 维持和平结构与第一导电结构和第二导电结构中的至少一个分离，形成用于自对准双图案化（“SADP”）工艺的导线的固定间隔距离。

公开(公告)号：US20220367519A1

公开(公告)日：2022-11-17

申请号：US17875257

申请日：2022-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Chi-Yu LU ,  Ting-Yu CHEN ,  Li-Chun TIEN

IPC: H01L27/118 ,  H01L27/02

Abstract: A method is provided, and including operations as below: forming multiple active areas extending in a first direction; forming multiple conductive patterns extending in a second direction different from the first direction and arranged in a first layer above the active areas; forming multiple gates extending parallel to the conductive patterns; and forming a first set of conductive lines extending in the first direction and arranged in three first metal tracks that are in a second layer above the first layer, wherein one of the first set of conductive lines is arranged in a middle track of the three first metal tracks, coupled to one of the gates and overlap a first shallow trench region between two of the active areas.

公开(公告)号：US20220359512A1

公开(公告)日：2022-11-10

申请号：US17875060

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei PENG ,  Hui-Zhong ZHUANG ,  Jiann-Tyng TZENG ,  Li-Chun TIEN ,  Pin-Dai SUE ,  Wei-Cheng LIN

IPC: H01L27/092 ,  H03K17/687

Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20220359493A1

公开(公告)日：2022-11-10

申请号：US17873935

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC China Company Limited

Inventor： Xin-Yong WANG ,  Li-Chun TIEN ,  Chih-Liang CHEN

IPC: H01L27/02 ,  H01L21/768 ,  H01L23/522

Abstract: An integrated circuit includes a first transistor, a second transistor, a first power line, and a second power line. The first transistor has a first active region and a first gate structure, in which the first active region has a source region and a drain region on opposite sides of the first gate structure. The second transistor is below the first transistor, and has a second active region and a second gate structure, in which the second active region has a source region and a drain region on opposite sides of the second gate structure. The first power line is above the first transistor, in which the first power line is electrically connected to the source region of first active region. The second power line is below the second transistor, in which the second power line is electrically connected to the source region of second active region.

公开(公告)号：US20220093646A1

公开(公告)日：2022-03-24

申请号：US17025983

申请日：2020-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Guo-Huei WU ,  Chi-Yu LU ,  Ting-Yu CHEN ,  Li-Chun TIEN

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit is disclosure. The integrated circuit includes a first pair of power rails, a set of conductive lines arranged in the first layer parallel to the first pair of power rails, a first set of active areas. The integrated circuit further includes a first gate arranged along the second direction, between the first pair of power rails, and crossing the first set of active areas in a layout view, wherein the first gate is configured to be shared by a first transistor of a first type and a second transistor of a second type; and a second gate and a third gate, in which the second gate is configured to be a control terminal of a third transistor, and the third gate is configured to be a control terminal of a fourth transistor which is coupled to the control terminal of the third transistor.

公开(公告)号：US20210407985A1

公开(公告)日：2021-12-30

申请号：US16910658

申请日：2020-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Liang CHEN ,  Shun Li CHEN ,  Li-Chun TIEN ,  Ting Yu CHEN ,  Hui-Zhong ZHUANG

IPC: H01L27/02 ,  H01L27/092 ,  G06F30/392

Abstract: A method includes generating a layout diagram of a cell of an integrated circuit (IC), and storing the generated layout diagram on a non-transitory computer-readable medium. In the generating the layout diagram of the cell, a first active region is arranged inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is arranged inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region is arranged to overlap the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region.

公开(公告)号：US20210384187A1

公开(公告)日：2021-12-09

申请号：US17406663

申请日：2021-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jian-Sing LI ,  Guo-Huei WU ,  Hui-Zhong ZHUANG ,  Chih-Liang CHEN ,  Li-Chun TIEN

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  G06F30/392 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/786

Abstract: An integrated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first active area extending in a first direction in a first layer. The second transistor includes a second active area that is disposed in a second layer below the first layer and overlaps the first active area. The third transistor includes at least two third active areas extending in the first direction in the first layer. In the first direction, a boundary line of one of the at least two third active areas is aligned with boundary lines of the first and second active areas. The fourth transistor includes at least two fourth active areas that are disposed in the second layer and overlap the at least two third active areas.

公开(公告)号：US20190148407A1

公开(公告)日：2019-05-16

申请号：US15940191

申请日：2018-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Pen GUO ,  Carlos H. DIAZ ,  Lee-Chung LU ,  Li-Chun TIEN

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.