公开(公告)号：US20230325579A1

公开(公告)日：2023-10-12

申请号：US18334551

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Shinn-Sheng Yu ,  Jue-Chin Yu ,  Ping-Chieh Wu

IPC: G06F30/398 ,  G03F1/36 ,  G03F7/20

CPC classification number: G06F30/398 ,  G03F7/70433 ,  G03F1/36

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

公开(公告)号：US09411924B2

公开(公告)日：2016-08-09

申请号：US14051549

申请日：2013-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36

Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.

Abstract translation: 本公开涉及一种利用低OPC（光学邻近校正）周期时间改进图案密度的方法，以及相关联的装置。 在一些实施例中，该方法通过形成作为集成芯片的图形表示的集成芯片（IC）设计来执行。 识别IC设计中的一个或多个低图案密度区域具有导致处理失败的图案密度。 低图案密度区域是IC设计的一个子集。 通过在低图案密度区域内添加一个或多个虚拟形状，在低图案密度区域内调整图案密度。 然后对IC设计执行数据准备处理，以修改低图案密度区域内的一个或多个虚拟形状的形状。 通过将虚拟形状引入局部区域而不是整个集成芯片设计中，随后的数据准备过程的需求减少。

公开(公告)号：US12019974B2

公开(公告)日：2024-06-25

申请号：US18334551

申请日：2023-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Shinn-Sheng Yu ,  Jue-Chin Yu ,  Ping-Chieh Wu

IPC: G06F30/30 ,  G03F1/36 ,  G03F7/00 ,  G06F30/398

CPC classification number: G06F30/398 ,  G03F1/36 ,  G03F7/70433

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

公开(公告)号：US20220365419A1

公开(公告)日：2022-11-17

申请号：US17386737

申请日：2021-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Ming Chang ,  Shinn-Sheng Yu ,  Jue-Chin Yu ,  Ping-Chieh Wu

IPC: G03F1/36 ,  G03F7/20 ,  H01L21/027

Abstract: A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

公开(公告)号：US10049178B2

公开(公告)日：2018-08-14

申请号：US15170026

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/36

Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.