公开(公告)号：US20190122931A1

公开(公告)日：2019-04-25

申请号：US15793127

申请日：2017-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01L49/02 ,  H01F17/00 ,  H01L27/08 ,  H01L21/768 ,  H01L23/00 ,  H01F41/04

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit having an inductor with one or more turns arranged along vertical planes that intersect an underlying substrate. In some embodiments, the integrated circuit includes a plurality of conductive routing layers having conductive wires and conductive vias disposed within one or more dielectric structures abutting a first substrate. The plurality of conductive routing layers define an inductor having one or more turns respectively including a vertically extending segment arranged along a plane that intersects the first substrate. The vertically extending segment has a plurality of the conductive wires and the conductive vias.

公开(公告)号：US11792969B2

公开(公告)日：2023-10-17

申请号：US16046188

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Chih-Hung Hsieh

IPC: H01L27/11 ,  H01L27/02 ,  G06F30/392 ,  H01L29/417 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H10B10/12 ,  G06F30/392 ,  H01L27/0207 ,  H01L29/41775 ,  H01L21/823821

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

公开(公告)号：US11545495B2

公开(公告)日：2023-01-03

申请号：US15636832

申请日：2017-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Chih-Hung Hsieh

IPC: H01L27/11 ,  H01L27/02 ,  G06F30/392 ,  H01L29/417 ,  H01L21/8238

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

公开(公告)号：US11410972B2

公开(公告)日：2022-08-09

申请号：US16896348

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

公开(公告)号：US10790194B2

公开(公告)日：2020-09-29

申请号：US16584809

申请日：2019-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao

IPC: H01L21/822 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L27/06 ,  H01F17/00 ,  H01F41/04 ,  H01L21/768 ,  H01L27/08 ,  H01L49/02

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.

公开(公告)号：US20200303351A1

公开(公告)日：2020-09-24

申请号：US16896348

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L25/00 ,  H01L23/00 ,  H01L23/532

Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

公开(公告)号：US10535668B1

公开(公告)日：2020-01-14

申请号：US16654873

申请日：2019-10-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Chih-Hung Hsieh

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/265 ,  H01L21/311 ,  H01L21/768 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.

公开(公告)号：US10453852B2

公开(公告)日：2019-10-22

申请号：US16206539

申请日：2018-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Chih-Hung Hsieh

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/265 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: A plurality of gate stacks is formed over a substrate. The gate stacks are surrounded by a dielectric structure. A plurality of contact-line-blocking patterns is formed over the dielectric structure. The contact-line-blocking patterns are formed using three or more lithography masks. A plurality of trenches is formed in the dielectric structure. The contact-line-blocking patterns serve as protective masks for the dielectric structure to prevent trenches from being formed in portions of the dielectric structure underneath the contact-line-blocking patterns. The trenches are filled with a conductive material to form a plurality of contact lines of the SRAM device.

公开(公告)号：US12062679B2

公开(公告)日：2024-08-13

申请号：US17384956

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Shih-Han Huang

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/1469

Abstract: The present disclosure relates to an image sensor having an image sensing element surrounded by a BDTI structure, and an associated method of formation. In some embodiments, a first image sensing element and a second image sensing element are arranged next to one another within an image sensing die. A pixel dielectric stack is disposed along a back of the image sensing die overlying the image sensing elements. The pixel dielectric stack includes a first high-k dielectric layer and a second high-k dielectric layer. The BDTI structure is disposed between the first image sensing element and the second image sensing element and extends from the back of the image sensor die to a position within the image sensor die. The BDTI structure includes a trench filling layer surrounded by an isolation dielectric stack. The pixel dielectric stack has a composition different from that of the isolation dielectric stack.

公开(公告)号：US20230363134A1

公开(公告)日：2023-11-09

申请号：US18355889

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Han Huang ,  Chih-Hung Hsieh

IPC: G06F30/392 ,  H01L27/02 ,  H01L29/417 ,  H10B10/00

CPC classification number: H10B10/12 ,  G06F30/392 ,  H01L27/0207 ,  H01L29/41775 ,  H01L21/823821

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.