公开(公告)号：US20240063182A1

公开(公告)日：2024-02-22

申请号：US18501314

申请日：2023-11-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5385 ,  H01L25/50

Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

公开(公告)号：US20230343765A1

公开(公告)日：2023-10-26

申请号：US17804928

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Hsien-Wei Chen ,  Meng-Liang Lin ,  Ying-Ju Chen ,  Shuo-Mao Chen

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L25/105 ,  H01L25/50 ,  H01L23/5385 ,  H01L24/17 ,  H01L21/4857 ,  H01L25/18

Abstract: A method includes forming a first package component, which includes an interposer, and a first die bonded to a first side of the interposer. A second die is bonded to a second side of the interposer. The second die includes a substrate, and a through-via penetrating through the substrate. The method further includes bonding a second package component to the first package component through a first plurality of solder regions. The first package component is further electrically connected to the second package component through the through-via in the second die. The second die is further bonded to the second package component through a second plurality of solder regions.

公开(公告)号：US11610864B2

公开(公告)日：2023-03-21

申请号：US16984369

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Shin-Puu Jeng ,  Feng-Cheng Hsu

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate and an interposer substrate over the package substrate. The interposer substrate has a first surface facing the package substrate and a second surface opposite the first surface. A first semiconductor device is disposed on the first surface, and a second semiconductor device is disposed on the second surface. Conductive structures are disposed between the interposer substrate and the package substrate. The first semiconductor device is located between the conductive structures. A first side of the first semiconductor device is at a first distance from the most adjacent conductive structure, and a second side of the first semiconductor device is at a second distance from the most adjacent conductive structure. The first side is opposite the second side, and the first distance is greater than the second distance.

公开(公告)号：US20220367210A1

公开(公告)日：2022-11-17

申请号：US17371673

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Yi Lin ,  Yu-Hao Chen ,  Fong-Yuan Chang ,  Po-Hsiang Huang ,  Jyh Chwen Frank Lee ,  Shuo-Mao Chen

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

公开(公告)号：US20210217691A1

公开(公告)日：2021-07-15

申请号：US17218285

申请日：2021-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Der-Chyang Yeh ,  Chiung-Han Yeh

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56

Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.

公开(公告)号：US20210159182A1

公开(公告)日：2021-05-27

申请号：US16900174

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Yao Chuang ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/768

Abstract: Semiconductor devices and methods of manufacture are provided wherein multiple integrated passive devices are integrated together utilizing an integrated fan out process in order to form a larger device with a smaller footprint. In particular embodiments the multiple integrated passive devices are capacitors which, once stacked together, can be utilized to provide a larger overall capacitance than any single passive device can obtain with a similar footprint.

公开(公告)号：US20200328174A1

公开(公告)日：2020-10-15

申请号：US16915052

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Der-Chyang Yeh ,  Li-Hsien Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/525 ,  H01L21/56 ,  H01L23/538 ,  H01L21/768

Abstract: An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

公开(公告)号：US20200286878A1

公开(公告)日：2020-09-10

申请号：US16884046

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao Lin ,  Cheng-Yi Hong ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng ,  Shu-Shen Yeh ,  Kuang-Chun Lee

IPC: H01L25/18 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/24 ,  H01L25/00 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00

Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.

公开(公告)号：US10763239B2

公开(公告)日：2020-09-01

申请号：US15795276

申请日：2017-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuo-Mao Chen ,  Feng-Cheng Hsu ,  Han-Hsiang Huang ,  Hsien-Wen Liu ,  Shin-Puu Jeng ,  Hsiao-Wen Lee

IPC: H01L25/065 ,  H01L25/16 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/31

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

公开(公告)号：US10741404B2

公开(公告)日：2020-08-11

申请号：US15806342

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Shin-Puu Jeng

IPC: H01L21/304 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/28 ,  H01L21/02 ,  H01L21/67 ,  H01L21/78 ,  H01L21/683 ,  B28D5/00 ,  H01L23/498

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a RDL structure and a protection layer. The die includes a first surface and a second surface opposite to each other. The encapsulant is aside the die. The RDL structure is electrically connected to the die though a plurality of conductive bumps. The RDL structure is underlying the second surface of the die and the encapsulant. The protection layer is located over the first surface of the die and the encapsulant. The protection layer is used for controlling the warpage of the package structure.