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公开(公告)号：US11664279B2
公开(公告)日：2023-05-30
申请号：US16939610
申请日：2020-07-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Hung Huang , Kuo-Feng Yu , Jian-Hao Chen , Shan-Mei Liao , Jer-Fu Wang , Yung-Hsiang Chan
IPC: H01L21/8234 , H01L29/51 , H01L27/088 , H01L21/28
CPC classification number: H01L21/823462 , H01L21/28185 , H01L27/0886 , H01L29/517
Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
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公开(公告)号：US11271783B2
公开(公告)日：2022-03-08
申请号：US17116792
申请日：2020-12-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Wen-Hung Huang
Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
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公开(公告)号：US10277215B2
公开(公告)日：2019-04-30
申请号：US15581033
申请日：2017-04-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Meng-Ting Tsai , Chien-Chun Tsai , Mu-Shan Lin , Wen-Hung Huang , Yu-Chi Chen
Abstract: Digital controlled delay lines are provided. A digital controlled delay line includes a plurality of delay cells coupled in a chain forming a propagation path to propagate an input signal and to delay the input signal by a delay time. The propagation path is formed when a single delay cell is operated in a feedback mode, the delay cells previous to the single delay cell in the chain are operated in a propagation mode, a subsequent delay cell following the single delay cell in the chain is operated in a standby mode, and the delay cells following the first subsequent delay cell in the chain are operated in an idle mode.
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公开(公告)号：US20240387277A1
公开(公告)日：2024-11-21
申请号：US18783597
申请日：2024-07-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Hung Huang , Kuo-Feng Yu , Jian-Hao Chen , Shan-Mei Liao , Jer-Fu Wang , Yung-Hsiang Chan
IPC: H01L21/8234 , H01L21/28 , H01L27/088 , H01L29/51
Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.
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公开(公告)号：US11652673B2
公开(公告)日：2023-05-16
申请号：US17677213
申请日：2022-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Wen-Hung Huang
CPC classification number: H04L25/03057 , H04L25/0212
Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
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Patent Agency Ranking
公开(公告)号：US20220182264A1
公开(公告)日：2022-06-09
申请号：US17677213
申请日：2022-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun YANG , Wen-Hung Huang
Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
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公开(公告)号：US10164758B2
公开(公告)日：2018-12-25
申请号：US15386342
申请日：2016-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun Yang , Mu-Shan Lin , Wen-Hung Huang
Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.
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公开(公告)号：US20180152279A1
公开(公告)日：2018-05-31
申请号：US15386342
申请日：2016-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shu-Chun YANG , Mu-Shan Lin , Wen-Hung Huang
IPC: H04L7/00
CPC classification number: H04L7/0008 , G06F13/00 , H04L7/0045 , H04L7/0091
Abstract: An electronic system includes transmitting circuitry of a first clock domain and receiving circuitry of a second domain. The transmitting circuitry re-times a digital input signal with rising edges of a clocking signal of the first clock domain when a phase of the clocking signal of the first clock domain leads a phase of a clocking signal associated with the digital input signal. Otherwise, the transmitting circuitry re-times the digital input signal with falling edges of the clocking signal of the first clock domain when the phase of the clocking signal of the first clock domain does not lead the phase of the clocking signal associated with a digital input signal. The receiving circuitry receives the re-timed digital input signal from the transmitting circuitry. Thereafter, the receiving circuitry re-times the re-timed digital input signal with rising edges of a phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal leads a phase of a clocking signal of the second clock domain. Otherwise, the receiving circuitry re-times the re-timed digital input signal with falling edges of the phase of a clocking signal associated with the re-timed digital input signal when the phase of the clocking signal associated with the re-timed digital input signal does not lead the phase of a clocking signal of the second clock domain.
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公开(公告)号：US09766288B2
公开(公告)日：2017-09-19
申请号：US15000553
申请日：2016-01-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wen-Hung Huang , Chien-Chun Tsai , Ying-Yu Hsu
IPC: G01R19/00 , G01R31/317
CPC classification number: G01R31/31708 , G01R31/31711
Abstract: A system for capturing an eye diagram is disclosed. In various embodiments, the system includes: a delay line arranged to receive a digital signal and output a time delayed version of the digital signal; an edge detection circuit arranged to receive the digital signal and the time delayed version of the digital signal, the edge detection circuit operating to output a signal corresponding to a logical value of the digital signal received coincident with an edge of the time delay version of the digital signal; a voltage comparator arranged to receive the digital signal and a reference voltage, the voltage comparator operating to output a first signal when a voltage of the digital signal and the reference voltage are equal to each other; and a controller that includes: an edge detection circuit receiver connected to receive the output signal from the edge detection circuit; a delay line control circuit connected to provide a delay time control signal to the delay line; a voltage comparator receiver connected to receive the first signal from the voltage comparator; and a voltage control unit connected to provide a controlled voltage to the voltage comparator.
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公开(公告)号：US20140195728A1
公开(公告)日：2014-07-10
申请号：US13736195
申请日：2013-01-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ying-Yu Hsu , Chien-Chun Tsai , Wen-Hung Huang
IPC: G06F12/02
CPC classification number: G06F13/1689 , G06F1/12 , G06F11/1604 , G06F11/1679 , G06F12/0246
Abstract: The present disclosure relates to an interface comprising a memory controller and a memory unit coupled to the memory controller and configured to communicate with the memory controller through a first signal and a second signal. The interface further comprises a determination unit comprising judgment logic configured to send a control signal configured to align the first signal with the second signal. The memory controller further comprises a digitally-controlled delay line (DCDL) coupled to the determination unit and configured to receive the control signal, wherein the determination unit instructs the DCDL to adjust a delay of the first signal to align the first signal with the second signal. The memory controller further comprises a value register configured to store a signal delay value corresponding to alignment between the first signal with the second signal which is contained within the control signal. Other devices and methods are disclosed.
Abstract translation: 本公开涉及一种包括存储器控制器和存储器单元的接口，该存储器单元耦合到存储器控制器，并被配置为通过第一信号和第二信号与存储器控制器进行通信。 接口还包括确定单元，其包括判定逻辑，该判定逻辑被配置为发送被配置为使第一信号与第二信号对准的控制信号。 存储器控制器还包括耦合到确定单元并被配置为接收控制信号的数字控制延迟线（DCDL），其中确定单元指示DCDL调整第一信号的延迟以将第一信号与第二信号对准 信号。 存储器控制器还包括值寄存器，其被配置为存储对应于第一信号与包含在控制信号内的第二信号之间的对准的信号延迟值。 公开了其他装置和方法。
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