公开(公告)号：US10510544B2

公开(公告)日：2019-12-17

申请号：US15726019

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ling Hsu ,  Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Shihkuang Yang

IPC: H01L21/28 ,  H01L21/3105 ,  H01L23/31 ,  H01L27/11531 ,  H01L29/423 ,  H01L45/00 ,  H01L27/11521 ,  H01L27/24 ,  H01L27/11548

Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.

公开(公告)号：US09997524B2

公开(公告)日：2018-06-12

申请号：US15272067

申请日：2016-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Tsun-Kai Tsao ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair

IPC: H01L29/788 ,  H01L27/11521

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

Abstract: A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.

公开(公告)号：US20160035736A1

公开(公告)日：2016-02-04

申请号：US14445697

申请日：2014-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Yong-Shiuan Tsair ,  Tsun-Kai Tsao ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu

IPC: H01L27/115 ,  H01L29/06 ,  H01L29/49 ,  H01L21/321 ,  H01L21/027 ,  H01L21/28 ,  H01L21/762 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825

Abstract: The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.

Abstract translation: 本公开涉及非易失性存储器单元结构以及相关联的方法。 非易失性存储单元包括两个彼此间隔开的晶体管，浮置栅极通过浮栅连接在一起。 在操作期间，非易失性存储单元被编程并从一个第一晶体管擦除并从另一个第二晶体管读取。 由于两个晶体管的浮置栅极连接在一起并与其他环境层绝缘，所以可以从第一晶体管控制存储的电荷并影响第二晶体管的阈值。

公开(公告)号：US20160013195A1

公开(公告)日：2016-01-14

申请号：US14326562

申请日：2014-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsun-Kai Tsao ,  Yong-Shiuan Tsair ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L23/528 ,  H01L21/28273 ,  H01L21/32137 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 半导体结构还包括位于第一源极/漏极区域上方的擦除栅极以及位于第一和第二源极/漏极区域之间的位于半导体衬底之上的字线和浮置栅极。 浮栅位于字线与擦除栅之间。 此外，浮动栅极包括从浮动栅极的顶表面垂直向上延伸并且分别布置在浮动栅极的相对侧上的一对突起。 还提供了使用高选择性蚀刻配方制造半导体结构的方法，例如主要由溴化氢（HBr）和氧组成的蚀刻配方。

公开(公告)号：US08928060B2

公开(公告)日：2015-01-06

申请号：US13891281

申请日：2013-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Shiuan Tsair ,  Wen-Ting Chu ,  Po-Wei Liu ,  Wen-Tuo Huang

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/66825 ,  H01L27/11517

Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing isolated source regions that are diffused only in the active regions between the stacked control gate structures. The architecture contains no CS under the isolation region, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. A metal layer is disposed along the semiconductor body above the common source regions to provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. Hence, this particular architecture reduces the resistance and the metal connection over several cells in an array suppresses the area over head.

Abstract translation: 本公开的一些实施例涉及通过利用仅在堆叠的控制栅极结构之间的有源区域中扩散的隔离源极区域来创建具有较低公共源（CS）电阻和降低的单元尺寸的分离栅极闪存单元的架构 。 该架构在隔离区域内不包含CS，从而消除CS舍入和CS电阻的影响，导致阵列中的单元之间的空间减小。 金属层沿共同源极区域上方的半导体本体设置，以在编程和擦除期间提供电位耦合，从而沿着形成CS线的方向电连接存储器单元的公共源。 因此，这种特定的架构降低了电阻，并且阵列中的几个单元的金属连接抑制了磁头上的区域。

公开(公告)号：US11127827B2

公开(公告)日：2021-09-21

申请号：US16248881

申请日：2019-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ling Hsu ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/40 ,  H01L21/265 ,  H01L29/66 ,  H01L29/788 ,  H01L21/3213 ,  H01L21/28

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

公开(公告)号：US20200098877A1

公开(公告)日：2020-03-26

申请号：US16248881

申请日：2019-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ling Hsu ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin ,  Shih Kuang Yang

IPC: H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/265 ,  H01L29/66 ,  H01L29/788 ,  H01L29/40

Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.

公开(公告)号：US20190355731A1

公开(公告)日：2019-11-21

申请号：US15981056

申请日：2018-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC: H01L27/11521 ,  H01L29/788 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/027 ,  H01L21/308

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

公开(公告)号：US10269818B2

公开(公告)日：2019-04-23

申请号：US15914485

申请日：2018-03-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsun-Kai Tsao ,  Hung-Ling Shih ,  Po-Wei Liu ,  Shun-Shing Yang ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  S.K. Yang

IPC: H01L27/11529 ,  H01L21/28 ,  H01L21/3105 ,  H01L29/423 ,  H01L27/11521

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

公开(公告)号：US10269815B2

公开(公告)日：2019-04-23

申请号：US15498743

申请日：2017-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang Yang ,  Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair

IPC: H01L21/04 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3065

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°