公开(公告)号：US11081403B2

公开(公告)日：2021-08-03

申请号：US16393543

申请日：2019-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522

Abstract: A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.

公开(公告)号：US10672665B2

公开(公告)日：2020-06-02

申请号：US16251642

申请日：2019-01-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shang-Wen Chang ,  Yi-Hsiung Lin ,  Yi-Hsun Chiu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/768

Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.

公开(公告)号：US20200098631A1

公开(公告)日：2020-03-26

申请号：US16531232

申请日：2019-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L21/768 ,  G06F17/50

Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

公开(公告)号：US10096597B1

公开(公告)日：2018-10-09

申请号：US15626204

申请日：2017-06-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Chung-Cheng Wu ,  Guo-Yung Chen ,  Yi-Hsiung Lin ,  Shang-Wen Chang ,  Yi-Hsun Chiu

IPC: H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a gate structure including a gate dielectric layer and a first gate electrode layer, and a second gate electrode layer. In the method for fabricating the semiconductor device, at first, the semiconductor substrate is provided. The semiconductor substrate includes fin portions. Then, a gate dielectric layer is formed on the fin portions. Thereafter, a first gate electrode layer is formed on the gate dielectric layer. Then, the first gate electrode layer is etched. Thereafter, a second electrode layer is formed on the first gate electrode layer. Therefore, the gate electrode layer formed on the gate dielectric layer is regrown with easy control.

公开(公告)号：US20250087632A1

公开(公告)日：2025-03-13

申请号：US18405718

申请日：2024-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chao Chou ,  Ching-Wei Tsai ,  Yi-Hsun Chiu

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528

Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die bonded over the first semiconductor die. The second semiconductor die includes a first backside interconnect structure having a first power rail structure. An integrated voltage regulator die is bonded over the second semiconductor die such that the integrated voltage regulator die is electrically connected to the first power rail structure. A through via is on the first semiconductor die and is electrically coupled to the first semiconductor die. The through via is disposed outside of and adjacent to the second semiconductor die. The through via also electrically couples the first semiconductor die to the second semiconductor die through the integrated voltage regulator die.

公开(公告)号：US12080713B2

公开(公告)日：2024-09-03

申请号：US18358140

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L21/768 ,  H01L23/535 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/7682 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US11682590B2

公开(公告)日：2023-06-20

申请号：US17391271

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiung Lin ,  Yi-Hsun Chiu ,  Shang-Wen Chang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/823871 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L23/5226 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.

公开(公告)号：US20220359303A1

公开(公告)日：2022-11-10

申请号：US17874267

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi Chuang ,  Li-Zhen Yu ,  Yi-Hsun Chiu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate; a metal gate structure disposed over a channel region of the semiconductor fin; a first interlayer dielectric (ILD) layer disposed over a source/drain (S/D) region next to the channel region of the semiconductor fin; and a first conductive feature including a first conductive portion disposed on the metal gate structure and a second conductive portion disposed on the first ILD layer, wherein a top surface of the first conductive portion is below a top surface of the second conductive portion, a first sidewall of the first conductive portion connects a lower portion of a first sidewall of the second conductive portion.

公开(公告)号：US11437385B2

公开(公告)日：2022-09-06

申请号：US16526415

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hao Wang ,  Yi-Hsun Chiu ,  Yi-Hsiung Lin ,  Shang-Wen Chang

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/417 ,  H01L21/762 ,  H01L29/423 ,  G11C11/412

Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.

公开(公告)号：US20220262794A1

公开(公告)日：2022-08-18

申请号：US17733169

申请日：2022-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768 ,  H01L29/417 ,  H01L29/66 ,  H01L23/535

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.