公开(公告)号：US11594615B2

公开(公告)日：2023-02-28

申请号：US17216448

申请日：2021-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Yu-Lin Yang ,  Wei-Sheng Yun ,  Chen-Feng Hsu ,  Tzu-Chiang Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/04 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

公开(公告)号：US20220216301A1

公开(公告)日：2022-07-07

申请号：US17656258

申请日：2022-03-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Hung-Li Chiang ,  Yu-Lin Yang ,  Chih Chieh Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/786 ,  H01L21/306 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

公开(公告)号：US11195926B2

公开(公告)日：2021-12-07

申请号：US16681102

申请日：2019-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Yu-Lin Yang ,  I-Sheng Chen ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786

Abstract: A gate-all-around structure including a first transistor is provided. The first transistor includes a semiconductor substrate having a top surface, and a first nanostructure over the top surface of the semiconductor substrate and between a first source and a first drain. The first transistor also includes a first gate structure around the first nanostructure, and an inner spacer between the first gate structure and the first source, wherein an interface between the inner spacer and the first gate structure is non-flat. The first transistor includes an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain.

公开(公告)号：US10727344B2

公开(公告)日：2020-07-28

申请号：US16049273

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Chih Chieh Yeh ,  Cheng-Hsien Wu ,  Hung-Li Chiang ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Tsung-Lin Lee ,  Yu-Lin Yang ,  I-Sheng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/165

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

公开(公告)号：US12211895B2

公开(公告)日：2025-01-28

申请号：US17202237

申请日：2021-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/06 ,  B82Y10/00 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers, the second semiconductor layer and an upper portion of the fin structure at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, are etched. A dielectric layer is formed over the etched upper portion of the fin structure. A source/drain epitaxial layer is formed. The source/drain epitaxial layer is connected to ends of the second semiconductor wires, and a bottom of the source/drain epitaxial layer is separated from the fin structure by the dielectric layer.

公开(公告)号：US11677010B2

公开(公告)日：2023-06-13

申请号：US17080575

申请日：2020-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Chiang ,  Chen-Feng Hsu ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Yu-Lin Yang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/0245 ,  H01L21/02172 ,  H01L21/02236 ,  H01L21/31056 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

公开(公告)号：US11309385B2

公开(公告)日：2022-04-19

申请号：US16939726

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Hung-Li Chiang ,  Yu-Lin Yang ,  Chih Chieh Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L29/06 ,  H01L21/82 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/786 ,  H01L21/306 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L21/3065

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

公开(公告)号：US11205706B2

公开(公告)日：2021-12-21

申请号：US16657873

申请日：2019-10-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin Yang ,  Tung Ying Lee ,  Shao-Ming Yu ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chao-Hsien Huang

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/31 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/764 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/775

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

公开(公告)号：US11177179B2

公开(公告)日：2021-11-16

申请号：US16914747

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Liang Chen ,  Tzu-Chiang Chen ,  Ta-Pen Guo ,  Yu-Lin Yang ,  I-Sheng Chen ,  Szu-Wei Huang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  G03F1/38 ,  H01L21/308 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/08 ,  H01L29/78 ,  H01L29/775 ,  H01L29/417 ,  H01L29/786 ,  H01L27/092 ,  H01L21/8238

Abstract: In a method, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layers are etched at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed. A dielectric layer is formed at the first source/drain space, thereby covering the exposed second semiconductor layers. The dielectric layer and part of the second semiconductor layers are etched, thereby forming a second source/drain space. A source/drain epitaxial layer is formed in the second source/drain space. At least one of the second semiconductor layers is in contact with the source/drain epitaxial layer, and at least one of the second semiconductor layers is separated from the source/drain epitaxial layer.

公开(公告)号：US20210335676A1

公开(公告)日：2021-10-28

申请号：US17368550

申请日：2021-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chen-Feng Hsu ,  Yu-Lin Yang ,  Tung Ying Lee ,  Chih Chieh Yeh

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/775 ,  H01L29/08 ,  H01L21/8234 ,  B82Y10/00

Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.