公开(公告)号：US20220359731A1

公开(公告)日：2022-11-10

申请号：US17870292

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

公开(公告)号：US20220208989A1

公开(公告)日：2022-06-30

申请号：US17699362

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chung-I Yang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

公开(公告)号：US12237414B2

公开(公告)日：2025-02-25

申请号：US17314815

申请日：2021-05-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

公开(公告)号：US12174545B2

公开(公告)日：2024-12-24

申请号：US18361254

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-Yu Chen ,  Sagar Deepak Khivsara ,  Kuo-An Liu ,  Chieh Hsieh ,  Shang-Chieh Chien ,  Gwan-Sin Chang ,  Kai Tak Lam ,  Li-Jui Chen ,  Heng-Hsin Liu ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: G03F7/00

Abstract: A photolithography system utilizes tin droplets to generate extreme ultraviolet radiation for photolithography. The photolithography system irradiates the droplets with a laser. The droplets become a plasma and emit extreme ultraviolet radiation. The photolithography system senses contamination of a collector mirror by the tin droplets and adjusts the flow of a buffer fluid to reduce the contamination.

公开(公告)号：US12009408B2

公开(公告)日：2024-06-11

申请号：US17870292

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66795 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/0653 ,  H01L29/6656

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

公开(公告)号：US20230387301A1

公开(公告)日：2023-11-30

申请号：US18447483

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Wen-Yuan Chen ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/0259 ,  H01L21/26526 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78696

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

公开(公告)号：US20230155008A1

公开(公告)日：2023-05-18

申请号：US18155392

申请日：2023-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Chia-Ying Su ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L27/0924 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/7851

Abstract: Embodiments of the present disclosure includes a semiconductor device. The semiconductor device includes first suspended nanostructures vertically stacked over one another and disposed on a substrate, a first gate stack engaging the first suspended nanostructures, a first gate spacer disposed on sidewalls of the first gate stack, second suspended nanostructures vertically stacked over one another and disposed on the substrate, a second gate stack engaging the second suspended nanostructures, and a second gate spacer disposed on sidewalls of the second gate stack. A middle portion of the first suspended nanostructures has a first thickness measured in a direction perpendicular to a top surface of the substrate. A middle portion of the second suspended nanostructures has a second thickness measured in the direction. The second thickness is smaller than the first thickness.

公开(公告)号：US11489063B2

公开(公告)日：2022-11-01

申请号：US16931930

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/08 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain trench; laterally etching the first semiconductor layers through the source/drain trench; forming an inner spacer layer, in the source/drain trench, at least on lateral ends of the etched first semiconductor layers; forming a seeding layer on the inner spacer layer; and growing a source/drain epitaxial layer in the source/drain trench, wherein the growing of the source/drain epitaxial layer includes growing the source/drain epitaxial layer from the seeding layer.

公开(公告)号：US20210305249A1

公开(公告)日：2021-09-30

申请号：US17347218

申请日：2021-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Tsai ,  Yu-Xuan Huang ,  Kuan-Lun Cheng ,  Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265 ,  H01L21/266 ,  H01L21/74 ,  H01L29/66 ,  H01L29/10

Abstract: The present disclosure provides an integrated circuit that includes a circuit formed on a semiconductor substrate; and a de-cap device formed on the semiconductor substrate and integrated with the circuit. The de-cap device includes a filed-effect transistor (FET) that further includes a source and a drain connected through contact features landing on the source and drain, respectively; a gate stack overlying a channel and interposed between the source and the drain; and a doped feature disposed underlying the channel and connecting to the source and the drain, wherein the doped feature is doped with a dopant of a same type of the source and the drain.

公开(公告)号：US20230123846A1

公开(公告)日：2023-04-20

申请号：US18066373

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Wei Ju Lee ,  Chun-Fu Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a stack of first semiconductor layers and second semiconductor layers over a substrate, etching the stack to form a source/drain (S/D) recess in exposing the substrate, and forming an S/D formation assistance region in the S/D recess. The S/D formation assistance region is partially embedded in the substrate and includes a semiconductor seed layer embedded in an isolation layer. The isolation layer electrically isolates the semiconductor seed layer from the substrate. The method also includes epitaxially growing an S/D feature in the S/D recess from the semiconductor seed layer. The S/D feature is in physical contact with the second semiconductor layers.