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公开(公告)号：US11145339B2
公开(公告)日：2021-10-12
申请号：US16881380
申请日：2020-05-22
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yung-Chow Peng
摘要： A computing device and method are provided. The computing device in some examples includes multiple digital-to-analog converters (DACs) having outputs connected to respective operational amplifiers, with outputs connected to the gates of respective transistors, each forming a serial combination with a respective memory element. The serial combinations are connected between a voltage reference point and a conductive line. An analog-to-digital converter is connected to the conductive line at the input. The DACs generate analog signals having ON-period lengths corresponding to the respective numbers at the DACs' inputs. The transistors generate currents indicative of the levels of output signals of the respective DACs and memory states of the respective memory elements for the ON-periods. The combined currents charge or discharge the conductive line to a voltage indicative of the sum of the numbers weighted by the memory states. The voltage is converted to a digital representation of the weighted sum.
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公开(公告)号：US20160091916A1
公开(公告)日：2016-03-31
申请号：US14502861
申请日：2014-09-30
发明人： Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
摘要： A device includes a bandgap reference stage, a mirror current source, a voltage control circuit, and a resistive device. The mirror current source has a control terminal electrically coupled to an internal node of the bandgap reference stage. The voltage control circuit includes a first terminal electrically coupled to a second internal node of the bandgap reference stage, and a second terminal electrically coupled to a first terminal of the mirror current source. The resistive device has a first terminal electrically coupled to a third terminal of the voltage control circuit.
摘要翻译： 器件包括带隙参考级，反射镜电流源，电压控制电路和电阻器件。 镜电流源具有电耦合到带隙基准级的内部节点的控制端子。 电压控制电路包括电耦合到带隙基准级的第二内部节点的第一端子和电耦合到反射镜电流源的第一端子的第二端子。 电阻装置具有电耦合到电压控制电路的第三端子的第一端子。
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公开(公告)号：US12087389B2
公开(公告)日：2024-09-10
申请号：US17874534
申请日：2022-07-27
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yung-Chow Peng , Szu-Chun Tsao
CPC分类号： G11C7/1057 , G06F7/5443 , G11C7/062 , G11C7/1084 , H03M1/462
摘要： In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.
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公开(公告)号：US12068747B2
公开(公告)日：2024-08-20
申请号：US17718456
申请日：2022-04-12
发明人： Szu-Lin Liu , Bei-Shing Lien , Yi-Wen Chen , Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
CPC分类号： H03K3/011 , H03F3/45475
摘要： A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.
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公开(公告)号：US20230421124A1
公开(公告)日：2023-12-28
申请号：US18232526
申请日：2023-08-10
发明人： Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
CPC分类号： H03F3/45076 , G11C7/12 , H03M1/38 , H03F2203/45156
摘要： Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.
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公开(公告)号：US20230387871A1
公开(公告)日：2023-11-30
申请号：US18446031
申请日：2023-08-08
发明人： Chin-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
CPC分类号： H03F3/45076 , G11C7/12 , H03M1/38 , H03F2203/45156
摘要： Disclosed herein are related to a method of amplifying an input voltage based on cascaded charge pump boosting. The method includes generating, at a set of capacitors, an input voltage corresponding to input data. The method further includes storing, by a first capacitor, first electrical charges corresponding to the input voltage to obtain a second voltage. The method further includes amplifying, a voltage amplifier, the second voltage according to the first electrical charges stored by the first capacitor to obtain a third voltage. The method further includes storing, by a second capacitor, second electrical charges according to the third voltage. The method further includes amplifying, by the voltage amplifier, the third voltage according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.
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公开(公告)号：US11756950B2
公开(公告)日：2023-09-12
申请号：US17363355
申请日：2021-06-30
发明人： Chin-Ho Chang , Yi-Wen Chen , Jaw-Juinn Horng , Yung-Chow Peng
IPC分类号： H01L27/02 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/823871 , H01L27/092
摘要： An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.
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公开(公告)号：US20230178605A1
公开(公告)日：2023-06-08
申请号：US17545825
申请日：2021-12-08
发明人： Jaw-Juinn Horng , Yi-Wen Chen , Chin-Ho Chang , Po-Yu Lai , Yung-Chow Peng
IPC分类号： H01L29/06 , H01L27/088 , H01L29/40
CPC分类号： H01L29/0696 , H01L27/088 , H01L29/401
摘要： A device including at least one transistor cell including metal-oxide semiconductor field-effect transistors each having drain/source terminals and a channel length. The at least one transistor cell includes a first number of transistors of the metal-oxide semiconductor field-effect transistors connected in series, with one of the drain/source terminals of one of the first number of transistors connected to one of the drain/source terminals of another one of the first number of transistors and gates of the first number of transistors connected together. The at least one transistor cell configured to be used to provide a transistor having a longer channel length than the channel length of each of the metal-oxide semiconductor field-effect transistors.
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公开(公告)号：US20220366948A1
公开(公告)日：2022-11-17
申请号：US17874534
申请日：2022-07-27
发明人： Jaw-Juinn Horng , Chin-Ho Chang , Yung-Chow Peng , Szu-Chun Tsao
摘要： In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.
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公开(公告)号：US20220223579A1
公开(公告)日：2022-07-14
申请号：US17363355
申请日：2021-06-30
发明人： Chin-Ho Chang , Yi-Wen Chen , Jaw-Juinn Horng , Yung-Chow Peng
IPC分类号： H01L27/02 , H01L27/092 , H01L21/8238
摘要： An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.
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