-
公开(公告)号：US20110235457A1
公开(公告)日：2011-09-29
申请号：US13051149
申请日：2011-03-18
申请人： Yoshiharu Hirata
发明人： Yoshiharu Hirata
摘要： According to one embodiment, a semiconductor integrated circuit device is provided. The semiconductor integrated circuit device is provided with a plurality of booster circuits, a regulator and a plurality of switches. Each of the booster circuit receives an input voltage, boosts the input voltage, and generates a boosted voltage having a different value. The regulator is capable of generating a plurality of dropped voltages by dropping each boosted voltage from the booster circuits. The switches are connected between the booster circuits and the regulator. The switches provide the boosted voltages outputted from the booster circuits selectively to the regulator as a power-supply voltage.
摘要翻译： 根据一个实施例，提供一种半导体集成电路器件。 半导体集成电路器件设置有多个升压电路，调节器和多个开关。 每个升压电路接收输入电压，升压输入电压，并产生具有不同值的升压电压。 调节器能够通过降低来自升压电路的每个升压电压来产生多个下降的电压。 开关连接在升压电路和调节器之间。 开关将从升压电路输出的升压电压作为电源电压选择性地提供给调节器。
-
公开(公告)号：US20110205810A1
公开(公告)日：2011-08-25
申请号：US12882232
申请日：2010-09-15
CPC分类号： G11C16/30 , G11C16/0483 , G11C16/08
摘要： According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a plurality of memory cells is formed in the first well region. A second cell array including a plurality of memory cells is formed in the second well region. The third well region includes the first and second well regions. The bit line is connected to the memory cells included in the first cell array and the memory cells included in the second cell array. The column decoder is connected to the bit line.
摘要翻译： 根据一个实施例，非易失性半导体存储装置包括第一导电类型的第一阱区，第一导电类型的第二阱区，第二导电类型的第三阱区，位线和列解码器。 在第一阱区中形成包括多个存储单元的第一单元阵列。 在第二阱区域中形成包括多个存储单元的第二单元阵列。 第三阱区域包括第一和第二阱区域。 位线连接到包括在第一单元阵列中的存储单元和包括在第二单元阵列中的存储单元。 列解码器连接到位线。
-
公开(公告)号：US07116592B2
公开(公告)日：2006-10-03
申请号：US11130141
申请日：2005-05-17
申请人： Shinji Takeda , Yoshiharu Hirata , Naokazu Kuzuno
发明人： Shinji Takeda , Yoshiharu Hirata , Naokazu Kuzuno
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C16/04 , G11C29/44 , G11C29/50004 , G11C29/78 , G11C2029/0405
摘要： Data read out from each memory cell in a memory cell array is compared with an expected value by a comparator, and the quality of a memory cell is determined by performing program verify and erase verify. Based on the comparison result of the comparator, a detected defective cell is repaired by replacing it with a spare cell. Every time a defective cell is replaced with a spare cell, information on the defective cell is stored in a register, and whether a defective cell exists and whether the repair is possible are determined on the basis of the information. When the repair is possible, a control circuit is caused to execute control, and a detected defective cell is repaired by replacing it with a spare cell. When the repair is impossible, the defect repair stops.
摘要翻译： 通过比较器将存储单元阵列中的每个存储单元读出的数据与预期值进行比较，并通过执行程序验证和擦除验证来确定存储单元的质量。 基于比较器的比较结果，通过用备用单元替换检测到的缺陷单元进行修复。 每当有缺陷的单元被替换为备用单元时，有缺陷单元的信息被存储在寄存器中，并且是否存在缺陷单元以及是否可以修复是可能的。 当可以进行修理时，使控制电路执行控制，并通过用备用单元替换来检测检测到的故障单元。 修理不可能时，缺陷修复停止。
-
公开(公告)号：US20120072645A1
公开(公告)日：2012-03-22
申请号：US13049009
申请日：2011-03-16
申请人： Nozomi Kasai , Yoshiharu Hirata
发明人： Nozomi Kasai , Yoshiharu Hirata
IPC分类号： G06F12/02
CPC分类号： G11C16/3445
摘要： According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array with a block including word lines, and each word line connected to memory cells, a controller which controls a data erase of the memory cells in the block, and a verify circuit which verifies whether or not the data erase is completed. The controller comprises being executed a verification by the verify circuit after being executed a first block erase in a predetermined condition, being executed a second block erase continuously when the number of memory cells which are judged by the verification as a completion of the data erase is n (n is a natural number) or less, and being executed a page erase continuously when the number of memory cells which are judged by the verification as a completion of the data erase is more than n.
摘要翻译： 根据一个实施例，非易失性半导体存储器包括具有包括字线的块的存储单元阵列，并且连接到存储单元的每个字线，控制块中的存储器单元的数据擦除的控制器以及验证电路， 验证数据擦除是否完成。 该控制器包括在执行预定条件下的第一块擦除之后由验证电路执行验证，当通过作为数据擦除完成的验证判定的存储器单元的数量是连续执行第二块擦除时 n（n是自然数）或更小，并且当通过作为数据擦除的完成的验证判断的存储器单元的数量大于n时，连续执行页擦除。
-
公开(公告)号：US07876619B2
公开(公告)日：2011-01-25
申请号：US12368667
申请日：2009-02-10
申请人： Shinji Takeda , Yoshiharu Hirata
发明人： Shinji Takeda , Yoshiharu Hirata
CPC分类号： G11C16/0483 , G11C16/10
摘要： A semiconductor memory device comprises: a write circuit including a latch circuit configured by two inverters having a positive side power supply terminal supplied with a first voltage and a negative side power supply terminal supplied with a second voltage; and a write state machine controlling the first and second voltages. When writing data to a memory cell, the first voltage is changed to a second value that is lower than a first value. When writing data to a memory cell, the second voltage is changed to a third value that is lower than the second value. The write state machine lowers the second voltage to an intermediate value between the second value and the third value and, while maintaining this intermediate value, lowers the first voltage from the first value to the second value.
摘要翻译： 一种半导体存储器件，包括：写入电路，包括由具有提供有第一电压的正侧电源端子和被提供有第二电压的负侧电源端子的两个反相器构成的锁存电路; 以及控制第一和第二电压的写状态机。 当将数据写入存储单元时，将第一电压改变为低于第一值的第二值。 当将数据写入存储单元时，第二电压被改变为低于第二值的第三值。 写状态机将第二电压降低到第二值和第三值之间的中间值，并且在保持该中间值的同时，将第一电压从第一值降低到第二值。
-
16.发明授权Semiconductor memory device with MOS transistors each having floating gate and control gate 有权具有MOS晶体管的半导体存储器件分别具有浮动栅极和控制栅极公开(公告)号：US07505355B2
公开(公告)日：2009-03-17
申请号：US11733796
申请日：2007-04-11
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/08 , G11C11/005 , G11C16/0425 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/115
摘要： A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m
摘要翻译： 半导体存储器件包括存储单元阵列，字线和行解码器。 存储单元阵列包括排列成矩阵的存储单元。 存储单元包括具有电荷累积层的第一MOS晶体管和控制栅极和第二MOS晶体管。 字线连接第一MOS晶体管的控制栅极。 行解码器包括第一地址解码电路，第二地址解码电路和传输门。 第一地址解码电路解码n位行地址信号中的m位（m和n是满足表达式m
-
公开(公告)号：US6078074A
公开(公告)日：2000-06-20
申请号：US985182
申请日：1997-12-04
IPC分类号： H01L21/8247 , H01L21/3205 , H01L23/52 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/76 , H01L29/88
CPC分类号： H01L27/115
摘要： An n-type diffused layer is formed in a p-type semiconductor substrate. A control gate electrode of a memory cell MC is connected with a metal interconnect of a first layer and the metal interconnect is connected with the diffused layer. Moreover, a metal interconnect of the first layer is connected with a metal interconnect of a second layer. An interconnect of the second layer is connected with the output node of a row decoder.
摘要翻译： 在p型半导体衬底中形成n型扩散层。 存储单元MC的控制栅电极与第一层的金属互连连接，并且金属互连与扩散层连接。 此外，第一层的金属互连与第二层的金属互连连接。 第二层的互连与行解码器的输出节点连接。
-
公开(公告)号：US20060007739A1
公开(公告)日：2006-01-12
申请号：US11130141
申请日：2005-05-17
申请人： Shinji Takeda , Yoshiharu Hirata , Naokazu Kuzuno
发明人： Shinji Takeda , Yoshiharu Hirata , Naokazu Kuzuno
IPC分类号： G11C11/34
CPC分类号： G11C29/4401 , G11C16/04 , G11C29/44 , G11C29/50004 , G11C29/78 , G11C2029/0405
摘要： Data read out from each memory cell in a memory cell array is compared with an expected value by a comparator, and the quality of a memory cell is determined by performing program verify and erase verify. Based on the comparison result of the comparator, a detected defective cell is repaired by replacing it with a spare cell. Every time a defective cell is replaced with a spare cell, information on the defective cell is stored in a register, and whether a defective cell exists and whether the repair is possible are determined on the basis of the information. When the repair is possible, a control circuit is caused to execute control, and a detected defective cell is repaired by replacing it with a spare cell. When the repair is impossible, the defect repair stops.
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.016 秒)
