公开(公告)号：US08317896B2

公开(公告)日：2012-11-27

申请号：US12812154

申请日：2008-12-25

申请人： Tetsuya Homma ,  Tomoyuki Ubusawa ,  Tomoyuki Furuyama ,  Akihiro Morikaku ,  Kumpei Tanaka

发明人： Tetsuya Homma ,  Tomoyuki Ubusawa ,  Tomoyuki Furuyama ,  Akihiro Morikaku ,  Kumpei Tanaka

IPC分类号： C22B7/00 ,  B22F9/04

CPC分类号： C22B7/007 ,  C22B3/10 ,  C22B3/22 ,  C22B58/00 ,  C25C1/00 ,  C25C5/04 ,  G02F1/1343 ,  G02F2203/68 ,  H01J9/52 ,  Y02P10/234 ,  Y02P10/236 ,  Y02W30/828

摘要： A method of recycling useful metals is provided. The method enables useful metals including indium, zinc, yttrium, europium, lanthanum, terbium, gadolinium, antimony, lead, copper, tin, and silver to be recovered from wastes, such as wasted flat panel displays, and recycled economically with small energy consumption. The method of recycling useful metals includes: a step in which wastes comprising various flat panel displays, e.g., liquid-crystal display panels, are crushed/powdered; a step in which the resultant particles are dissolved in an aqueous hydrofluoric acid solution; and a step in which various metal oxides and various metal fluorides which remain undissolved are filtered off and the aqueous hydrofluoric acid solution containing various metal ions is electrolyzed to deposit and recover metals for transparent-electrode oxides, such as indium and zinc, and other useful metals.

摘要翻译： 提供了回收有用金属的方法。 该方法能够从诸如浪费的平板显示器等废弃物中回收有用的金属，包括铟，锌，钇，铕，镧，铽，钆，锑，铋，钆，锑，铅，铜，锡和银， 。 回收有用金属的方法包括：将包括各种平板显示器（例如液晶显示面板）的废物粉碎/粉碎的步骤; 将所得颗粒溶解在氢氟酸水溶液中的步骤; 将各种金属氧化物和保持未溶解的各种金属氟化物过滤并将含有各种金属离子的氢氟酸水溶液电解沉积并回收诸如铟和锌的透明电极氧化物的金属和其它有用的步骤 金属。

公开(公告)号：US6054383A

公开(公告)日：2000-04-25

申请号：US754327

申请日：1996-11-21

申请人： Mieko Suzuki ,  Tetsuya Homma

发明人： Mieko Suzuki ,  Tetsuya Homma

IPC分类号： H01L23/522 ,  H01L21/304 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76877

摘要： A fabrication method of a semiconductor device is provided, which enables the formation of a conductive plug in an opening of an interlevel dielectric layer without arising any void. After a first wiring layer is formed on a first interlevel electric layer, a second interlevel dielectric layer is formed on the first interlevel dielectric layer to cover the first wiring layer. A first opening is formed in the second interlevel dielectric layer. A first conductive layer is formed on or over the second interlevel dielectric layer to cover the first opening. A first protection layer is formed on the first conductive layer to cover a first depressed part of the first conductive layer. The first protection layer having a first buried part on the first depressed part. The first protection layer and the first conductive layer are polished by a CMP process until the second interlevel dielectric layer is exposed, thereby selectively leaving the first depressed part within the first opening. The first depressed part left within the first opening constitutes a first conductor plug for electrically interconnecting the first wiring layer with a second wiring layer formed to be contacted with the fist conductor plug.

摘要翻译： 提供一种半导体器件的制造方法，其能够在不产生任何空隙的情况下在层间电介质层的开口中形成导电插塞。 在第一层间电层上形成第一布线层之后，在第一层间电介质层上形成第二层间电介质层以覆盖第一布线层。 在第二层间介质层中形成第一开口。 第一导电层形成在第二层间介电层上或上方以覆盖第一开口。 第一保护层形成在第一导电层上以覆盖第一导电层的第一凹陷部分。 第一保护层在第一凹陷部分上具有第一掩埋部分。 通过CMP工艺对第一保护层和第一导电层进行抛光直到第二层间电介质层露出，从而选择性地将第一凹陷部分留在第一开口内。 留在第一开口内的第一凹部构成第一导体插头，用于将第一布线层与形成为与第一导体插塞接触的第二布线层电连接。

公开(公告)号：US5891234A

公开(公告)日：1999-04-06

申请号：US619086

申请日：1996-03-21

申请人： Kenichi Koyanagi ,  Koji Kishimoto ,  Tetsuya Homma

发明人： Kenichi Koyanagi ,  Koji Kishimoto ,  Tetsuya Homma

IPC分类号： H01L21/768 ,  C03C1/00 ,  H01L21/316 ,  C09D183/04

CPC分类号： C03C1/008

摘要： A spin on glass composition which includes in a solvent as a main component alkoxysilane represented by H.sub.n Si(OR).sub.4-n, where n is 1, 2, or 3 and R is an alkyl group. Water or alcohol is available as a solvent. It is preferable to add the above alkoxysilane with at least any one of a phosphorus compound, boron compound and a germanium compound. It is also preferable to add the above alkoxysilane not only with tetraalkoxysilane Si(OR).sub.4, where R is an alkyl group, but also with at least any one of phosphorus compound, boron compound and germanium compound.

摘要翻译： 在由H n Si（OR）4-n表示的主要成分的烷氧基硅烷的溶剂中包括n为1,2或3，R为烷基的旋涂玻璃组合物。 水或醇可作为溶剂使用。 优选使用磷化合物，硼化合物和锗化合物中的至少一种添加上述烷氧基硅烷。 另外，优选不仅与四烷氧基硅烷Si（OR）4（其中R为烷基），而且还与磷化合物，硼化合物和锗化合物中的至少一种相加。

公开(公告)号：US5405805A

公开(公告)日：1995-04-11

申请号：US943069

申请日：1992-09-10

申请人： Tetsuya Homma

发明人： Tetsuya Homma

IPC分类号： H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76801 ,  H01L21/76826 ,  H01L21/76828 ,  Y10S438/909

摘要： A method for forming a multi-level wiring structure for semiconductor devices includes the steps of forming inter-layer insulating films and exposing at least a part of such films to a vapor containing alkoxyfluorosilane. This enables the water content of silicon oxide films to be reduced, the quality thereof to be made higher and the production yield and the reliability of the product to be enhanced. The method for forming an insulating film includes the steps of exposing such film to a vapor containing alkoxyfluorometal as a major component and heat-treating the exposed film. The method for forming a surface protective film includes the steps of forming a silicon oxide film at a temperature of 250.degree. C. at most, applying to such film a coating solution for SOG, heat-treating the film at a temperature of 200.degree. C. at most, exposing the film to a vapor containing alkoxyfluorosilane as a major component, heat-treating at a temperature of 250.degree. C. to form a fluorine-containing silicon oxide film. Then, a silicon nitride film is formed at a temperature not higher than 250.degree. C. At low temperatures not higher than 250.degree. C., the film has a high flatness and no crack develops thereon and no hillock develops on aluminum wirings. All these contribute to the fabrication of highly reliable semiconductor devices.

摘要翻译： 一种用于形成半导体器件的多层布线结构的方法包括形成层间绝缘膜并将至少一部分这种膜暴露于含有烷氧基氟硅烷的蒸汽的步骤。 由此，能够降低氧化硅膜的水分含量，提高其质量，提高产品的产率和可靠性。 形成绝缘膜的方法包括以下步骤：将这种膜暴露于含有烷氧基氟金属作为主要成分的蒸气中，并对暴露的膜进行热处理。 形成表面保护膜的方法包括以下步骤：至多在250℃的温度下形成氧化硅膜，向该膜施加用于SOG的涂布溶液，在200℃的温度下对该膜进行热处理 最多将膜以含有烷氧基氟硅烷作为主要成分的蒸气曝光，在250℃的温度下进行热处理，形成含氟氧化硅膜。 然后，在不高于250℃的温度下形成氮化硅膜。在不高于250℃的低温下，该膜具有高的平坦度，并且在铝布线上不产生裂纹，并且不产生小丘。 所有这些都有助于制造高度可靠的半导体器件。

公开(公告)号：US5399529A

公开(公告)日：1995-03-21

申请号：US67094

申请日：1993-05-26

申请人： Tetsuya Homma

发明人： Tetsuya Homma

IPC分类号： H01L23/522 ,  H01L21/316 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76801 ,  H01L21/76828

摘要： Disclosed is a process for producing semiconductor devices of multilevel interconnection structure which are absolutely free from cracking in the insulator films and voids or disconnections in the aluminum wirings. After a fluorine-containing silicon oxide film 4 is formed at a temperature of 50.degree. C. or less using an alkoxyfluorosilane vapor and a water vapor, a spin-on glass film 5 is formed thereon by baking at a temperature of 200.degree. C. or less, which is exposed to the alkoxyfluorosilane vapor to effect condensation of the spin-on glass film at room temperature, and then an insulator film is formed thereon, using the thus treated spin-on glass film as a flattening material.

摘要翻译： 公开了一种制造多层互连结构的半导体器件的方法，其绝缘体绝缘体不会在铝布线中产生裂纹和空隙或断开。 在使用烷氧基氟硅烷蒸汽和水蒸汽在50℃以下的温度下形成含氟氧化硅膜4之后，在200℃的温度下进行烘烤，形成旋涂玻璃膜5。 暴露于烷氧基氟硅烷蒸气以在室温下进行旋涂玻璃膜的冷凝，然后使用如此处理的旋涂玻璃膜作为平坦化材料在其上形成绝缘膜。

公开(公告)号：US20110017020A1

公开(公告)日：2011-01-27

申请号：US12812154

申请日：2008-12-25

申请人： Tetsuya Homma ,  Tomoyuki Ubusawa ,  Tomoyuki Furuyama ,  Akihiro Morikaku ,  Kumpei Tanaka

发明人： Tetsuya Homma ,  Tomoyuki Ubusawa ,  Tomoyuki Furuyama ,  Akihiro Morikaku ,  Kumpei Tanaka

IPC分类号： C22B1/00

CPC分类号： C22B7/007 ,  C22B3/10 ,  C22B3/22 ,  C22B58/00 ,  C25C1/00 ,  C25C5/04 ,  G02F1/1343 ,  G02F2203/68 ,  H01J9/52 ,  Y02P10/234 ,  Y02P10/236 ,  Y02W30/828

摘要： A method of recycling useful metals is provided. The method enables useful metals including indium, zinc, yttrium, europium, lanthanum, terbium, gadolinium, antimony, lead, copper, tin, and silver to be recovered from wastes, such as wasted flat panel displays, and recycled economically with small energy consumption. The method of recycling useful metals includes: a step in which wastes comprising various flat panel displays, e.g., liquid-crystal display panels, are crushed/powdered; a step in which the resultant particles are dissolved in an aqueous hydrofluoric acid solution; and a step in which various metal oxides and various metal fluorides which remain undissolved are filtered off and the aqueous hydrofluoric acid solution containing various metal ions is electrolyzed to deposit and recover metals for transparent-electrode oxides, such as indium and zinc, and other useful metals.

摘要翻译： 提供了回收有用金属的方法。 该方法能够从诸如浪费的平板显示器等废弃物中回收有用的金属，包括铟，锌，钇，铕，镧，铽，钆，锑，铋，钆，锑，铅，铜，锡和银， 。 回收有用金属的方法包括：将包括各种平板显示器（例如液晶显示面板）的废物粉碎/粉碎的步骤; 将所得颗粒溶解在氢氟酸水溶液中的步骤; 将各种金属氧化物和保持未溶解的各种金属氟化物过滤并将含有各种金属离子的氢氟酸水溶液电解沉积并回收诸如铟和锌的透明电极氧化物的金属和其它有用的步骤 金属。

公开(公告)号：US5776829A

公开(公告)日：1998-07-07

申请号：US561881

申请日：1995-11-22

申请人： Tetsuya Homma ,  Makoto Sekine

发明人： Tetsuya Homma ,  Makoto Sekine

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522 ,  H01L21/441

CPC分类号： H01L21/76829

摘要： The present invention provides a novel method for forming multilevel interconnections in a semiconductor device. A silicon oxide film is formed on a semiconductor substrate. A first photo-resist film pattern is formed on the first silicon oxide film. The surface of the silicon oxide film covered with the photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a first fluoro-containing silicon oxide film on the silicon oxide film by use of the first photo-resist film pattern as a mask. The first photo-resist film pattern is removed, thereby resulting in first grooves in the fluoro-containing silicon oxide film. First interconnections are formed within the first grooves. An inter-layer insulator is formed on an entire surface of the device and then subjected to a dry etching and a photolithography to form via holes in the inter-layer insulator. Conductive films are selectively formed in the via holes. A second photo-resist film pattern is selectively formed to cover the conductive films within the via holes. The entire surface of the device covered with the second photo-resist film pattern is exposed to a super-saturated hydrosilicofluoric acid solution to selectively deposit a second fluoro-containing silicon oxide film on the inter-layer insulator by use of the second photo-resist film pattern as a mask. The second photo-resist film pattern is removed, thereby resulting in second grooves in the second fluoro-containing silicon oxide film. Second interconnections are formed within the second grooves.

摘要翻译： 本发明提供了一种用于在半导体器件中形成多层互连的新方法。 在半导体基板上形成氧化硅膜。 在第一氧化硅膜上形成第一光致抗蚀剂膜图案。 用光致抗蚀剂膜图案覆盖的氧化硅膜的表面暴露于超饱和氢硅氟酸溶液中，以通过使用第一光致抗蚀剂膜选择性地在氧化硅膜上沉积第一含氟氧化硅膜 模式作为面具。 除去第一光致抗蚀剂膜图案，从而在含氟氧化硅膜中形成第一凹槽。 第一互连形成在第一槽内。 在器件的整个表面上形成层间绝缘体，然后进行干蚀刻和光刻以在层间绝缘体中形成通孔。 导电膜选择性地形成在通孔中。 选择性地形成第二光致抗蚀剂膜图案以覆盖通孔内的导电膜。 覆盖有第二光致抗蚀剂膜图案的器件的整个表面暴露于超饱和氢硅氟酸溶液中，以通过使用第二光致抗蚀剂选择性地在层间绝缘体上沉积第二含氟氧化硅膜 电影模式作为面具。 除去第二光致抗蚀剂膜图案，从而在第二含氟氧化硅膜中形成第二槽。 第二互连形成在第二槽内。

公开(公告)号：US5607880A

公开(公告)日：1997-03-04

申请号：US53369

申请日：1993-04-28

申请人： Mieko Suzuki ,  Tetsuya Homma

发明人： Mieko Suzuki ,  Tetsuya Homma

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76825 ,  H01L23/5329 ,  H01L2924/0002

摘要： The invention provides a fabrication method of multilevel interconnections for semiconductor integrated circuits. Aluminium wiring lines are formed on a first silicon oxide film overlying a silicon substrate. A second silicon oxide film is grown by a plasma chemical vapor deposition on the wiring lines and the first silicon oxide film for a specific surface treatment of either an etching with use of fluorine compounds or an ion-implantation of fluorine compounds. A third silicon oxide film is grown on the second silicon oxide film by an atmospheric pressure chemical vapor deposition with use of organic silicon compounds and an oxygen including ozone.

摘要翻译： 本发明提供了一种用于半导体集成电路的多电平互连的制造方法。 铝布线形成在覆盖硅基板​​的第一氧化硅膜上。 通过等离子体化学气相沉积在布线和第一氧化硅膜上生长第二氧化硅膜，用于对使用氟化合物的蚀刻或氟化合物的离子注入进行比表面处理。 通过使用有机硅化合物和包含臭氧的氧气通过大气压化学气相沉积在第二氧化硅膜上生长第三氧化硅膜。

公开(公告)号：US5491108A

公开(公告)日：1996-02-13

申请号：US164580

申请日：1993-12-10

申请人： Mieko Suzuki ,  Tetsuya Homma ,  Yukinobu Murao ,  Takaho Tanigawa ,  Hiroki Koga

发明人： Mieko Suzuki ,  Tetsuya Homma ,  Yukinobu Murao ,  Takaho Tanigawa ,  Hiroki Koga

IPC分类号： H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76832

摘要： A method which can markedly improve the flatness of a semiconductor integrated circuit device by forming selectively a layer insulating film on an underlying substrate having level differences is disclosed. First, a Ti--W alloy film is formed on a member which brings about level differences due to wirings or the like, then a PECVD silicon oxide film is formed followed by a plasma treatment using CF.sub.4 gas. Further, a silicon oxide film is deposited by atmospheric pressure CVD using ozone and tetraethoxysilane. Then, the surface is flattened by etchback using an organic SOG film, and a silicon oxide film is formed by plasma excited CVD.

摘要翻译： 公开了一种能够通过在具有电平差的下层衬底上选择性地形成层间绝缘膜来显着提高半导体集成电路器件的平坦度的方法。 首先，在由于布线等引起的电位差的构件上形成Ti-W合金膜，然后形成PECVD氧化硅膜，然后使用CF 4气体进行等离子体处理。 此外，通过使用臭氧和四乙氧基硅烷的大气压CVD沉积氧化硅膜。 然后，通过使用有机SOG膜的回蚀使表面平坦化，并且通过等离子体激发CVD形成氧化硅膜。

公开(公告)号：US5420075A

公开(公告)日：1995-05-30

申请号：US45791

申请日：1993-04-14

申请人： Tetsuya Homma ,  Mieko Suzuki

发明人： Tetsuya Homma ,  Mieko Suzuki

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  Y10S438/98

摘要： A method of manufacturing a semiconductor device, incorporates the steps of: performing reactive ion etching using a fluorine compound gas to surface-treat the lower level wirings which permits selective deposition of the second silicon oxide film; selectively depositing a second silicon oxide film between said lower level wirings by a CVD method using an organic silicon compound gas and an oxidizable gas as source gases; depositing a third silicon oxide film on an entire surface and forming through holes connected to the lower wirings; and forming upper level wirings connected to the lower level wirings. Further, an additional silicon oxide film can be deposited on the major surface so as to form a side wall thereof on the lower level wirings. The reactive ion etching is then performed.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：使用氟化合物气体进行反应离子蚀刻以表面处理允许选择性沉积第二氧化硅膜的下层布线; 通过使用有机硅化合物气体和可氧化气体作为源气体的CVD方法在所述下层布线之间选择性地沉积第二氧化硅膜; 在整个表面上沉积第三氧化硅膜并形成连接到下布线的通孔; 并形成连接到下层布线的上层配线。 此外，可以在主表面上沉积另外的氧化硅膜，以在下层布线上形成其侧壁。 然后进行反应离子蚀刻。