公开(公告)号：US5491108A

公开(公告)日：1996-02-13

申请号：US164580

申请日：1993-12-10

申请人： Mieko Suzuki ,  Tetsuya Homma ,  Yukinobu Murao ,  Takaho Tanigawa ,  Hiroki Koga

发明人： Mieko Suzuki ,  Tetsuya Homma ,  Yukinobu Murao ,  Takaho Tanigawa ,  Hiroki Koga

IPC分类号： H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76832

摘要： A method which can markedly improve the flatness of a semiconductor integrated circuit device by forming selectively a layer insulating film on an underlying substrate having level differences is disclosed. First, a Ti--W alloy film is formed on a member which brings about level differences due to wirings or the like, then a PECVD silicon oxide film is formed followed by a plasma treatment using CF.sub.4 gas. Further, a silicon oxide film is deposited by atmospheric pressure CVD using ozone and tetraethoxysilane. Then, the surface is flattened by etchback using an organic SOG film, and a silicon oxide film is formed by plasma excited CVD.

摘要翻译： 公开了一种能够通过在具有电平差的下层衬底上选择性地形成层间绝缘膜来显着提高半导体集成电路器件的平坦度的方法。 首先，在由于布线等引起的电位差的构件上形成Ti-W合金膜，然后形成PECVD氧化硅膜，然后使用CF 4气体进行等离子体处理。 此外，通过使用臭氧和四乙氧基硅烷的大气压CVD沉积氧化硅膜。 然后，通过使用有机SOG膜的回蚀使表面平坦化，并且通过等离子体激发CVD形成氧化硅膜。

公开(公告)号：US6054383A

公开(公告)日：2000-04-25

申请号：US754327

申请日：1996-11-21

申请人： Mieko Suzuki ,  Tetsuya Homma

发明人： Mieko Suzuki ,  Tetsuya Homma

IPC分类号： H01L23/522 ,  H01L21/304 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76877

摘要： A fabrication method of a semiconductor device is provided, which enables the formation of a conductive plug in an opening of an interlevel dielectric layer without arising any void. After a first wiring layer is formed on a first interlevel electric layer, a second interlevel dielectric layer is formed on the first interlevel dielectric layer to cover the first wiring layer. A first opening is formed in the second interlevel dielectric layer. A first conductive layer is formed on or over the second interlevel dielectric layer to cover the first opening. A first protection layer is formed on the first conductive layer to cover a first depressed part of the first conductive layer. The first protection layer having a first buried part on the first depressed part. The first protection layer and the first conductive layer are polished by a CMP process until the second interlevel dielectric layer is exposed, thereby selectively leaving the first depressed part within the first opening. The first depressed part left within the first opening constitutes a first conductor plug for electrically interconnecting the first wiring layer with a second wiring layer formed to be contacted with the fist conductor plug.

摘要翻译： 提供一种半导体器件的制造方法，其能够在不产生任何空隙的情况下在层间电介质层的开口中形成导电插塞。 在第一层间电层上形成第一布线层之后，在第一层间电介质层上形成第二层间电介质层以覆盖第一布线层。 在第二层间介质层中形成第一开口。 第一导电层形成在第二层间介电层上或上方以覆盖第一开口。 第一保护层形成在第一导电层上以覆盖第一导电层的第一凹陷部分。 第一保护层在第一凹陷部分上具有第一掩埋部分。 通过CMP工艺对第一保护层和第一导电层进行抛光直到第二层间电介质层露出，从而选择性地将第一凹陷部分留在第一开口内。 留在第一开口内的第一凹部构成第一导体插头，用于将第一布线层与形成为与第一导体插塞接触的第二布线层电连接。

公开(公告)号：US5607880A

公开(公告)日：1997-03-04

申请号：US53369

申请日：1993-04-28

申请人： Mieko Suzuki ,  Tetsuya Homma

发明人： Mieko Suzuki ,  Tetsuya Homma

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76825 ,  H01L23/5329 ,  H01L2924/0002

摘要： The invention provides a fabrication method of multilevel interconnections for semiconductor integrated circuits. Aluminium wiring lines are formed on a first silicon oxide film overlying a silicon substrate. A second silicon oxide film is grown by a plasma chemical vapor deposition on the wiring lines and the first silicon oxide film for a specific surface treatment of either an etching with use of fluorine compounds or an ion-implantation of fluorine compounds. A third silicon oxide film is grown on the second silicon oxide film by an atmospheric pressure chemical vapor deposition with use of organic silicon compounds and an oxygen including ozone.

摘要翻译： 本发明提供了一种用于半导体集成电路的多电平互连的制造方法。 铝布线形成在覆盖硅基板​​的第一氧化硅膜上。 通过等离子体化学气相沉积在布线和第一氧化硅膜上生长第二氧化硅膜，用于对使用氟化合物的蚀刻或氟化合物的离子注入进行比表面处理。 通过使用有机硅化合物和包含臭氧的氧气通过大气压化学气相沉积在第二氧化硅膜上生长第三氧化硅膜。

公开(公告)号：US5420075A

公开(公告)日：1995-05-30

申请号：US45791

申请日：1993-04-14

申请人： Tetsuya Homma ,  Mieko Suzuki

发明人： Tetsuya Homma ,  Mieko Suzuki

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76801 ,  H01L21/76834 ,  Y10S438/98

摘要： A method of manufacturing a semiconductor device, incorporates the steps of: performing reactive ion etching using a fluorine compound gas to surface-treat the lower level wirings which permits selective deposition of the second silicon oxide film; selectively depositing a second silicon oxide film between said lower level wirings by a CVD method using an organic silicon compound gas and an oxidizable gas as source gases; depositing a third silicon oxide film on an entire surface and forming through holes connected to the lower wirings; and forming upper level wirings connected to the lower level wirings. Further, an additional silicon oxide film can be deposited on the major surface so as to form a side wall thereof on the lower level wirings. The reactive ion etching is then performed.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：使用氟化合物气体进行反应离子蚀刻以表面处理允许选择性沉积第二氧化硅膜的下层布线; 通过使用有机硅化合物气体和可氧化气体作为源气体的CVD方法在所述下层布线之间选择性地沉积第二氧化硅膜; 在整个表面上沉积第三氧化硅膜并形成连接到下布线的通孔; 并形成连接到下层布线的上层配线。 此外，可以在主表面上沉积另外的氧化硅膜，以在下层布线上形成其侧壁。 然后进行反应离子蚀刻。

公开(公告)号：US5468682A

公开(公告)日：1995-11-21

申请号：US355008

申请日：1994-12-13

申请人： Tetsuya Homma

发明人： Tetsuya Homma

IPC分类号： C09K3/14 ,  C01B33/18 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/463

CPC分类号： H01L21/31053

摘要： Disclosed herein is abrasives consisting of fine particles of fluorinated silicon oxide which do not contain alkali metal and methods of thier manufacture, and high yield and high reliability methods of manufacturing semiconductor devices by the use of these abrasives. The abrasive comprises a solution in which fine particles of fluorinated silicon oxide are dispersed is formed by addition of boric acid to an aqueous solution of hydrosilicofluoric acid or addition of pure water to an alcohol solution of alkoxyfluorosilane. By the use of these abrasives, a layer insulating film for multi-layer wiring can be flattened.

摘要翻译： 本文公开了由不含碱金属的氟化氧化硅微粒和其制造方法组成的研磨剂，以及通过使用这些研磨剂制造半导体器件的高产率和高可靠性方法。 研磨剂包括通过将硼酸加入到氢氟酸的水溶液中或者将纯水加入到烷氧基氟硅烷的醇溶液中而形成分散有氟化氧化硅微粒的溶液。 通过使用这些研磨剂，可以使用于多层布线的层绝缘膜变平。

公开(公告)号：US5288518A

公开(公告)日：1994-02-22

申请号：US894584

申请日：1992-06-05

申请人： Tetsuya Homma

发明人： Tetsuya Homma

IPC分类号： H01L21/316 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/50

CPC分类号： C23C16/45514 ,  C23C16/401 ,  C23C16/45561 ,  C23C16/45595

摘要： A chemical vapor deposition method for forming a fluorine-containing silicon oxide film comprises introducing a gaseous mixture of alkoxysilane or its polymers as a source gas with fluoroalkoxysilane added thereto into a reaction chamber and performing decomposition of the gaseous mixture to deposit the fluorine-containing silicon oxide film onto a substrate. During the formation of the fluorine-containing silicon oxide film, at least one of compounds containing phosphorus or boron such as organic phosphorus compounds and organic boron compounds may be evaporated and introduced into said gaseous mixture, thereby adding at least one of phosphorus and boron to said fluorine-containing silicon oxide film. The fluorine-containing oxide film may be formed by effecting the decomposition of the gaseous mixture in the presence of ozone gas, or under ultraviolet radiation, or gas plasma.

摘要翻译： 用于形成含氟氧化硅膜的化学气相沉积方法包括将作为源气体的烷氧基硅烷或其聚合物的气体混合物与添加了氟烷氧基硅烷的反应室引入反应室，并进行气态混合物的分解以沉积含氟硅 氧化膜到基板上。 在形成含氟氧化硅膜期间，可以将至少一种含有磷或硼的化合物如有机磷化合物和有机硼化合物蒸发并引入所述气态混合物中，从而将至少一种磷和硼添加到 所述含氟氧化硅膜。 含氟氧化物膜可以通过在臭氧气体的存在下或在紫外线下或气体等离子体下进行气体混合物的分解来形成。

公开(公告)号：US5521424A

公开(公告)日：1996-05-28

申请号：US361536

申请日：1994-12-22

申请人： Kazuyoshi Ueno ,  Tetsuya Homma

发明人： Kazuyoshi Ueno ,  Tetsuya Homma

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H01L23/58

CPC分类号： H01L21/02131 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31629 ,  H01L23/5329 ,  H01L2924/0002

摘要： The semiconductor device has a multilayer structure wherein a substantially pure silicon dioxide film containing substantially no fluorine atom and a silicon dioxide film containing fluorine atoms are sequentially laminated on a substrate. Etching rate of a silicon dioxide film depends on a fluorine concentration in the film, so that a suitable etch selectivity of the silicon dioxide film containing fluorine atoms from the substantially pure silicon dioxide film can be obtained to form an oxide trench used for a trench interconnection and a via-hole used for a via-plug. The oxide film containing fluorine atoms has as good a quality as the silicon dioxide film not containing impurities has, thereby obtaining a superior characteristic of the semiconductor device. Addition of fluorine atoms reduces a specific permittivity to thereby obtain a higher speed.

摘要翻译： 半导体器件具有多层结构，其中基本上不含氟原子的基本上纯的二氧化硅膜和含有氟原子的二氧化硅膜依次层压在基板上。 二氧化硅膜的蚀刻速率取决于膜中的氟浓度，从而可以获得从基本上纯的二氧化硅膜中含有氟原子的二氧化硅膜的合适蚀刻选择性，以形成用于沟槽互连的氧化物沟槽 以及用于通孔的通孔。 含有氟原子的氧化物膜的质量与不含杂质的二氧化硅膜具有良好的质量，从而获得了优异的半导体器件的特性。 氟原子的添加降低了比介电常数，从而获得更高的速度。

公开(公告)号：US5444023A

公开(公告)日：1995-08-22

申请号：US179718

申请日：1994-01-11

申请人： Tetsuya Homma

发明人： Tetsuya Homma

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76829 ,  H01L21/76826

摘要： A spin coated insulating film is coated selectively between wirings by treating the surface of a wiring layer with a fluorine compound gas plasma. The spin on glass film is made compact by exposing it to fluoroalkoxysilane vapor to accelerate condensation and polymerization of the spin coated materials. A silicon oxide film is formed by plasma excited CVD to form a flat interlayer insulating film. A fine mutilayer wiring structure can be readily formed by employing the above mentioned planarizing method of the interlayer insulating film.

摘要翻译： 通过用氟化合物气体等离子体处理布线层的表面，在布线之间选择性地涂布旋涂绝缘膜。 通过将其旋涂在氟代烷氧基硅烷蒸气上以加速旋涂层的冷凝和聚合，从而使玻璃膜上的旋涂变得紧凑。 通过等离子体激发CVD形成氧化硅膜以形成平坦的层间绝缘膜。 通过采用上述层间绝缘膜的平面化方法可以容易地形成精细的三层布线结构。

公开(公告)号：US5215787A

公开(公告)日：1993-06-01

申请号：US820254

申请日：1992-01-14

申请人： Tetsuya Homma

发明人： Tetsuya Homma

IPC分类号： H01L21/283 ,  C23C16/40 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02131 ,  H01L21/31625 ,  H01L21/76801

摘要： It is an object of the present invention to provide an excellent silicon oxide film formed at a temperature of 200.degree. C. or less, a method of forming the silicon oxide film, and a selective growing method. According to the present invention, by using a vapor containing alkoxyfluorosilane as a main component, a silicon oxide film containing fluorine is formed at a temperature of 200.degree. C. or less in a reaction chamber having a predetermined temperature and a predetermined pressure. In addition, an organic film such as a photoresist film is used as a mask to selectively form the silicon oxide film. Although the silicon oxide film containing fluorine and formed on the basis of the present invention is formed at a very low temperature of 30.degree. C., this silicon oxide film has a water content smaller than that of a silicon oxide film formed at a temperature of 250.degree. C. in a conventional method. In addition, the film properties of the silicon oxide film according to the present invention are better than those of the silicon oxide film formed in the conventional method. Furthermore, a two-layered aluminum wiring structure can be easily formed by the selective growing method.

公开(公告)号：US5840631A

公开(公告)日：1998-11-24

申请号：US562991

申请日：1995-11-27

申请人： Akira Kubo ,  Tetsuya Homma ,  Koji Kishimoto

发明人： Akira Kubo ,  Tetsuya Homma ,  Koji Kishimoto

IPC分类号： C23C16/40 ,  H01L21/205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/443

CPC分类号： H01L21/02164 ,  C23C16/401 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02277 ,  H01L21/31612 ,  H01L21/76801 ,  H01L2924/0002

摘要： A method of manufacturing a semiconductor device includes the following steps. A lower wiring layer is formed on a semiconductor substrate through an insulating film. A compound gas having a catalysis for promoting formation of silicon oxide is added in an atmosphere using a main component gas consisting of ozone, water vapor, and one of alkoxysilane and organosiloxane as a source gas to form a silicon oxide film by a chemical vapor deposition (CVD) method directly on a surface of the semiconductor substrate on which the lower wiring layer is formed. An upper wiring layer is formed on the silicon oxide film.

摘要翻译： 一种制造半导体器件的方法包括以下步骤。 通过绝缘膜在半导体衬底上形成下布线层。 在气氛中使用由臭氧，水蒸气和烷氧基硅烷和有机硅氧烷之一组成的主要成分气体作为源气体，在气氛中加入具有促进氧化硅形成的催化剂的复合气体，通过化学气相沉积法形成氧化硅膜 （CVD）方法直接在其上形成下布线层的半导体衬底的表面上。 在氧化硅膜上形成上部布线层。