公开(公告)号：US12184297B2

公开(公告)日：2024-12-31

申请号：US18159305

申请日：2023-01-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: H03M1/06

Abstract: A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.

公开(公告)号：US12074600B2

公开(公告)日：2024-08-27

申请号：US17949446

申请日：2022-09-21

Applicant: Texas Instruments Incorporated

Inventor： Robin Hoel ,  Anuvrat Srivastava ,  Aniruddha P N ,  Anand Kumar G

IPC: H03K21/10 ,  G06F1/08 ,  G06F1/10

CPC classification number: H03K21/10 ,  G06F1/08 ,  G06F1/10

Abstract: An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.

公开(公告)号：US12013436B2

公开(公告)日：2024-06-18

申请号：US18175730

申请日：2023-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

IPC: G01R31/3185 ,  G06F21/31 ,  G06F21/45 ,  H04L9/40

CPC classification number: G01R31/318536 ,  G06F21/31 ,  G06F21/45 ,  H04L63/1433

Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

公开(公告)号：US11847466B2

公开(公告)日：2023-12-19

申请号：US17537952

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Robin Osa Hoel ,  Anand Kumar G

IPC: G06F9/4401

CPC classification number: G06F9/4401

Abstract: In described examples, an integrated circuit (IC) includes a first temperature sensor, a processor, a second temperature sensor, and a reset module. The first sensor senses a first body temperature of the IC. The processor asserts a thermal shutdown signal if the first body temperature exceeds a first threshold. In response to the thermal shutdown signal, the second sensor asserts a reset request signal and senses a second body temperature of the IC. If the second body temperature is less than a second threshold, the second sensor asserts a reset end signal. The reset module outputs a system reset signal to the first sensor and the processor if the reset request signal is asserted, and outputs a system recovery signal if the reset end signal is asserted. The first sensor and the processor deactivate if the system reset signal is asserted, and activate if the system recovery signal is asserted.

公开(公告)号：US11824550B2

公开(公告)日：2023-11-21

申请号：US17565797

申请日：2021-12-30

Applicant: Texas Instruments Incorporated

Inventor： Anand Kumar G ,  Srinivasa B S Chakravarthy ,  Aniruddha Periyapatna Nagendra

IPC: H03M1/12

CPC classification number: H03M1/1225 ,  H03M1/1245

Abstract: A method is provided. In some examples, the method includes receiving, at a sequencer circuit of an analog-to-digital converter (ADC), a first request to perform a first conversion. In addition, the method includes determining, by the sequencer circuit, that the ADC is not busy. The method further includes responsive to determining that the ADC is not busy, and by the sequencer circuit, causing the ADC to perform the first conversion. The method also includes receiving, at the sequencer circuit, a second request to perform a second conversion. The method includes determining, by the sequencer circuit, that the ADC is busy and, responsive to determining that the ADC is busy, and by the sequencer circuit, waiting to cause the ADC to perform the second conversion.

公开(公告)号：US20230317123A1

公开(公告)日：2023-10-05

申请号：US17710879

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: G11C7/10 ,  G11C7/22 ,  G11C5/14

CPC classification number: G11C7/109 ,  G11C7/1063 ,  G11C7/222 ,  G11C7/1039 ,  G11C5/14

Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

公开(公告)号：US20230102099A1

公开(公告)日：2023-03-30

申请号：US17563398

申请日：2021-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan RAJU ,  Sudhakar SURENDRAN ,  Anand Kumar G

IPC: G06F11/14 ,  G06F11/07 ,  G06F13/40 ,  G06F13/16 ,  G06F21/60

Abstract: This disclosure relates to an electronic device. The electronic device includes a non-transitory storage device, one or more peripherals, wherein the one or more peripherals are disabled, a processor configured to transmit a request to enable a peripheral of the one or more peripherals, and a power reset manager module. The power reset manager module is configured to receive the request to enable the peripheral. The power reset manager module includes a first memory configured to store, in response to the received request, an indication that peripheral was enabled. The processor is further configured to copy contents of the first memory to the non-transitory storage device and output the indication that the peripheral was enabled as a part of an update procedure.

公开(公告)号：US20230091498A1

公开(公告)日：2023-03-23

申请号：US17482676

申请日：2021-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Veeramanikandan RAJU ,  Anand Kumar G ,  Prachi MISHRA

IPC: G06F12/10 ,  G06F13/10

Abstract: A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

公开(公告)号：US20220342749A1

公开(公告)日：2022-10-27

申请号：US17378570

申请日：2021-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Kumar G

IPC: G06F11/10 ,  G06F13/28

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

公开(公告)号：US20220269225A1

公开(公告)日：2022-08-25

申请号：US17409029

申请日：2021-08-23

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan RAJU ,  Anand Kumar G

IPC: G05B9/02 ,  G06F11/14 ,  G06F13/20 ,  G06F9/4401

Abstract: Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.