公开(公告)号：US09991329B2

公开(公告)日：2018-06-05

申请号：US15209696

申请日：2016-07-13

Applicant: Texas Instruments Incorporated

Inventor： Christoph Andreas Othmar Dirnecker ,  Wolfgang Schwartz ,  Doug Weiser ,  Joel Martin Halbert ,  Joseph Anthony DeSantis ,  Karsten Jens Spinger

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/268

CPC classification number: H01L28/24 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/32051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528

Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.

公开(公告)号：US10770538B2

公开(公告)日：2020-09-08

申请号：US15976357

申请日：2018-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christoph Andreas Othmar Dirnecker ,  Wolfgang Schwartz ,  Doug Weiser ,  Joel Martin Halbert ,  Joseph Anthony DeSantis ,  Karsten Jens Spinger

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/268

Abstract: A method of forming an electronic device includes forming an opening through a dielectric layer located over a first resistive layer, the first resistive layer having a first sheet resistance. A second resistive layer is deposited over the dielectric layer and into the opening. The second resistive layer has a second sheet resistance different from the first sheet resistance. A portion of the second resistive layer is removed, thereby forming first and second noncontiguous portions of the second resistive layer, wherein the second portion of the second resistive layer contacts the first resistive layer.

公开(公告)号：US20190019884A1

公开(公告)日：2019-01-17

申请号：US15999542

申请日：2018-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L29/808 ,  H01L29/10 ,  H01L21/265 ,  H01L23/535 ,  H01L21/324 ,  H01L29/06

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

公开(公告)号：US10079294B2

公开(公告)日：2018-09-18

申请号：US15195287

申请日：2016-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/808

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

公开(公告)号：US20180019297A1

公开(公告)日：2018-01-18

申请号：US15209696

申请日：2016-07-13

Applicant: Texas Instruments Incorporated ,  TEXAS INSTRUMENTS DEUTSCHLAND GMBH

Inventor： Christoph Andreas Othmar Dirnecker ,  Wolfgang Schwartz ,  Doug Weiser ,  Joel Martin Halbert ,  Joseph Anthony DeSantis ,  Karsten Jens Spinger

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/268 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/3205 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L28/24 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/32051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528

Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.

公开(公告)号：US20170373171A1

公开(公告)日：2017-12-28

申请号：US15195287

申请日：2016-06-28

Applicant: Texas Instruments Incorporated

Inventor： Alexei Sadovnikov ,  Doug Weiser ,  Mattias Erik Dahlstrom ,  Joel Martin Halbert

IPC: H01L29/66 ,  H01L23/535 ,  H01L21/324 ,  H01L29/808 ,  H01L21/265

CPC classification number: H01L29/66916 ,  H01L21/265 ,  H01L21/324 ,  H01L23/535 ,  H01L29/0692 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/808 ,  H01L29/8086

Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

公开(公告)号：US09412879B2

公开(公告)日：2016-08-09

申请号：US14327157

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Xiaochuan Bi ,  Tracey L. Krakowski ,  Doug Weiser

IPC: H01L29/66 ,  H01L29/864 ,  H01L29/165

CPC classification number: H01L29/864 ,  H01L27/0635 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66159

Abstract: A method to integrate a vertical IMPATT diode in a planar process.

Abstract translation: 在平面过程中集成垂直IMPATT二极管的方法。